PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 40

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

Table 4
Pin No.
64
62
55
Data Sheet
SCLKX
Symbol
SYPX
XDI
Pin Definitions - System Interface (cont’d)
Input (I)
Output (O)
Supply (S)
I
I
I
Function
Synchronous Pulse Transmit
Defines the beginning of time slot 0 at system
highway port XDI together with the values of
XC0.XCO, XC1.XTO and XC1.XCOS. Sampling
is done with the falling edge of SCLKX.
The pulse cycle is an integer multiple of 125 µs.
System Clock Transmit
Working clock for the transmit system interface
with a frequency of 8.192 MHz (SIC1.SXSC = 0,
SIC1.SRSC = 0) or 2.048 MHz (E1)/1.544 MHz
(T1/J1) (SIC1.SXSC = 1, SIC1.SRSC = 1).
Transmit Data In
Transmit data received from the system
highway. Latching of data is done with the falling
transitions of SCLKX.
E1 data rate (SCLKX = 8.192 MHz):
FMR1.IMOD = 0: 4096 kbit/s
FMR1.IMOD = 1: 2048 kbit/s
E1 data rate (SCLKX = 2.048MHz):
FMR1.IMOD = 1 & SIC1.SXSC = 1: 2048kbit/s
T1/J1data rate (SCLKX = 8.192 MHz):
FMR1.IMOD = 0: 4096 kbit/s
FMR1.IMOD = 1 & SIC1.SXSC = 0: 2048 kbit/s
T1/J1data rate (SCLKX = 1.544 MHz):
FMR1.IMOD = 1 & SIC1.SXSC = 1: 1544 kbit/s
The delay between the beginning of time slot 0
and the initial edge of SCLKX (after SYPX goes
active) is determined by the values of transmit
time slot offset (XC1.XTO5-0), transmit clock
slot offset (XC0.XCO2-0) and XC1.XCOS.
40
Pin Descriptions
FALC-LH V1.3
PEB 2255
2000-07