DS33X82+ Maxim Integrated Products, DS33X82+ Datasheet - Page 334
DS33X82+
Manufacturer Part Number
DS33X82+
Description
IC MAPPING ETHERNET 256CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33X11.pdf
(375 pages)
Specifications of DS33X82+
Applications
Data Transport
Interface
Serial
Voltage - Supply
1.8V, 2.5V, 3.3V
Package / Case
256-CSBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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The figure below demonstrates the TSYNC pulse configured to arrive 2 clock cycles before the byte boundary
through the use of the LI.TCR register.
Figure 11-12. Transmit Serial Port Interface with VCAT, early TSYNC (2 cycles)
Figure 11-13 shows the basic functional timing relationship for the receive serial port interface. RCLK may be
gapped during Framing Overhead positions or to support Fractional T1/E1/T3/E3, as shown in Figure 11-15. The
RSYNC signal must be provided to the device as a frame, multiframe, or byte boundary indication. VCAT
applications require a multiframe boundary. The expected position of the RSYNC pulse is not programmable, and
must be provided as indicated. Note that the first clock after the RSYNC will sample the LSB of the last byte of the
previous frame.
Figure 11-13. Receive Serial Port Interface, without VCAT, rising edge sampling
Figure 11-14. Receive Serial Port Interface with VCAT, rising edge sampling
Figure 11-15. Receive Serial Port Interface with Gapped Clock (T1)
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
TSYNC
RSYNC
RSYNC
RSYNC
RDATA
RDATA
RDATA
TDATA
TCLK
RCLK
RCLK
RCLK
LSB
LSB
LSB Fbit
MSB
MSB
Encapsulated Ethernet Data
MSB
MSB
VCAT OH
Encapsulated Ethernet Data
VCAT OH
MSB
MSB
Encapsulated Ethernet Data
Encapsulated Ethernet Data
MSB
MSB
Encapsulated Ethernet Data
Encapsulated Ethernet Data
MSB
MSB
Encapsulated Ethernet Data
Encapsulated Ethernet Data
MSB
MSB
Encapsulated Ethernet
Encapsulated Ethernet
334 of 375
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