DK-SI-5SGXEA7/ES Altera, DK-SI-5SGXEA7/ES Datasheet - Page 378
DK-SI-5SGXEA7/ES
Manufacturer Part Number
DK-SI-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-SI-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2724
- Current page: 378 of 530
- Download datasheet (16Mb)
1–6
Figure 1–7. CDR PLL in Stratix V Devices
Stratix V Device Handbook Volume 3: Transceivers
rx_serial_data
signal detect
Clock Data Recovery Unit
refclk
Channel PLL
The transmitter PMA includes the following features:
■
■
■
■
■
■
■
The PMA of each receiver channel includes a channel PLL that you can configure as a
CMU PLL or receiver CDR that generates the serial transceiver clocks.
Figure 1–7
Each receiver channel has a channel PLL that you can configure as an independent
CDR unit to recover the clock from the incoming serial data stream. The serial and
parallel recovered clocks are used to clock the receiver PMA and PCS blocks.
The CDR supports the full range of data rates. The voltage-controlled oscillator (VCO)
operates at half rate. The L-counter dividers after the VCO extend the CDR’s data rate
range. The settings are automatically chosen by the Quartus II software.
The CDR operates in either lock-to-reference (LTR) or lock-to-data (LTD) mode. In
LTR mode, the CDR tracks the input reference clock. In LTD mode, the CDR tracks the
incoming serial data.
“Transmitter Output Buffer” on page 1–15
“Programmable Transmitter Termination” on page 1–15
“Programmable Output Differential Voltage” on page 1–16
“Programmable Pre-Emphasis” on page 1–16
“Serializer” on page 1–16
“PCIe Receiver Detect” on page 1–17
“PCIe Electrical Idle” on page 1–17
/N
shows a CDR PLL.
Frequency
Controller
LTR/LTD
Detector
Detector
Phase
Phase
(PFD)
(PD)
Up
Up
Down
Down
Charge Pump
Loop Filter
&
Chapter 1: Transceiver Architecture in Stratix V Devices
Controlled
Oscillator
Voltage
Detect
(VCO)
Lock
/M
/2
/L
May 2011 Altera Corporation
pma_rx_is_lockedtoref
Serial Clock
Recovered Clock
PMA Architecture
Related parts for DK-SI-5SGXEA7/ES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: