DK-SI-5SGXEA7/ES Altera, DK-SI-5SGXEA7/ES Datasheet - Page 496

• Manufacturer Part Number: DK-SI-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-SI-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2724

4–40
Figure 4–30. XAUI Configuration Datapath
Note to
(1) Standard PCS in a low latency configuration is used in this configuration. Additionally, a portion of the PCS is implemented in soft logic.
Stratix V Device Handbook Volume 3: Transceivers
Channel 0
Channel 1
Channel 2
16
Channel 3
Figure
Supported Features
4–30:
20
16
Figure 4–30
Stratix V transceivers support the following features in a XAUI configuration.
64-Bit SDR Interface to the MAC/RS
Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between
the XAUI PCS and the Ethernet MAC/RS. It requires each of the four XAUI lanes to
transfer 8-bit data and 1-bit wide control code at both the positive and negative edge
(DDR) of the 156.25 MHz interface clock.
FPGA Fabric
20
20
shows the transceiver datapath in a XAUI configurations.
20
Soft PCS
Soft PCS
Soft PCS
Soft PCS
(Note 1)
20
Channel 0
Channel 1
Channel 2
Channel 3
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
20
20
Transmitter Standard PCS
Transmitter Standard PCS
Receiver Standard PCS
Transmitter Standard PCS
Transmitter Standard PCS
10
10
May 2011 Altera Corporation
Transmitter PMA Ch0
Transmitter PMA Ch1
Transmitter PMA Ch2
Receiver PMA
Transmitter PMA Ch3
XAUI