MT46V64M8BN-6 L:FTR Micron Technology Inc, MT46V64M8BN-6 L:FTR Datasheet - Page 57
![](/photos/31/34/313422/mfg557-60-fbga_sml.jpg)
MT46V64M8BN-6 L:FTR
Manufacturer Part Number
MT46V64M8BN-6 L:FTR
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V64M8BN-6_LFTR.pdf
(91 pages)
Specifications of MT46V64M8BN-6 L:FTR
Organization
64Mx8
Density
512Mb
Address Bus
15b
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Package Type
FBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
175mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
CAS Latency (CL)
Figure 24:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
CAS Latency
Note:
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first bit of output data. The latency can be set to 2, 2.5, or 3 (-5B
only) clocks, as shown in Figure 24. Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Table 35 on page 58 indi-
cates the operating frequencies at which each CL setting can be used.
Command
Command
Command
BL = 4 in the cases shown; shown with nominal
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
READ
READ
READ
T0
T0
T0
CL = 2
CL = 3
CL = 2.5
NOP
NOP
NOP
T1
T1
T1
57
Transitioning Data
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
NOP
NOP
T2
T2
T2
512Mb: x4, x8, x16 DDR SDRAM
T2n
T2n
t
AC,
t
DQSCK, and
NOP
NOP
NOP
T3
T3
T3
Don’t Care
T3n
T3n
T3n
©2000 Micron Technology, Inc. All rights reserved.
t
DQSQ.
Operations