ADC101S021EVAL National Semiconductor, ADC101S021EVAL Datasheet - Page 10

• Manufacturer Part Number: ADC101S021EVAL
• Manufacturer: National Semiconductor

Specifications of ADC101S021EVAL

• Lead Free Status / Rohs Status: Not Compliant

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Applications Information
1.0 ADC101S021 OPERATION
The ADC101S021 is a successive-approximation analog-to-
digital converter designed around a charge-redistribution dig-
ital-to-analog converter core. Simplified schematics of the
ADC101S021 in both track and hold modes are shown in
Figure 3 and Figure 4, respectively. In Figure 3, the device is
in track mode: switch SW1 connects the sampling capacitor
to the input and SW2 balances the comparator inputs. The
device is in this state until CS is brought low, at which point
the device moves to the hold mode.
2.0 USING THE ADC101S021
The serial interface timing diagram for the ADC101S021 is
shown in Figure 2. CS is chip select, which initiates conver-
sions on the ADC101S021 and frames the serial data trans-
fers. SCLK (serial clock) controls both the conversion process
and the timing of serial data. SDATA is the serial data out pin,
where a conversion result is found as a serial data stream.
Basic operation of the ADC101S021 begins with CS going
low, which initiates a conversion process and data transfer.
Subsequent rising and falling edges of SCLK will be labelled
with reference to the falling edge of CS; for example, "the third
falling edge of SCLK" shall refer to the third falling edge of
SCLK after CS goes low.
At the fall of CS, the SDATA pin comes out of TRI-STATE and
the converter moves from track mode to hold mode. The input
signal is sampled and held for conversion on the falling edge
of CS. The converter moves from hold mode to track mode
FIGURE 3. ADC101S021 in Track Mode
FIGURE 4. ADC101S021 in Hold Mode
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Figure 4 shows the device in hold mode: switch SW1 con-
nects the sampling capacitor to ground, maintaining the sam-
pled voltage, and switch SW2 unbalances the comparator.
The control logic then instructs the charge-redistribution DAC
to add or subtract fixed amounts of charge from the sampling
capacitor until the comparator is balanced. When the com-
parator is balanced, the digital word supplied to the DAC is
the digital representation of the analog input voltage. The de-
vice moves from hold mode to track mode on the 13th rising
edge of SCLK.
on the 13th rising edge of SCLK (see Figure 2). The SDATA
pin will be placed back into TRI-STATE after the 16th falling
edge of SCLK, or at the rising edge of CS, whichever occurs
first. After a conversion is completed, the quiet time (t
must be satisfied before bringing CS low again to begin an-
other conversion.
Sixteen SCLK cycles are required to read a complete sample
from the ADC101S021. The sample bits (including leading or
trailing zeroes) are clocked out on falling edges of SCLK, and
are intended to be clocked in by a receiver on subsequent
rising edges of SCLK. The ADC101S021 will produce three
leading zero bits on SDATA, followed by ten data bits, most
significant first. After the data bits, the ADC101S021 will clock
out two trailing zeros.
If CS goes low before the rising edge of SCLK, an additional
(fourth) zero bit may be captured by the next falling edge of
SCLK.
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