LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 334

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

September 2008
Introduction
The memory in LatticeECP™ and LatticeEC™ FPGAs is built using volatile SRAM. When the power is removed,
the SRAM cells lose their contents. A supporting non-volatile memory is required to configure the device on power-
up and at any time the device needs to be updated. The LatticeECP/EC devices support a sysCONFIG™ interface
that provides multiple configuration modes as well as the dedicated ispJTAG™ port and boundary scan. The differ-
ent programming modes are listed below.
• SPI
• SPIX
• Master Serial
• Slave Serial
• Master Parallel
• Slave Parallel
• ispJTAG (1149.1 Interface)
This technical note covers all the configuration options available for LatticeECP/EC devices.
Configuration Pins
The LatticeECP/EC devices support two types of sysCONFIG pins, dedicated and dual-purpose. The dedicated
pins are used exclusively for configuration; the dual-purpose pins are available as extra I/O pins. If a dual-purpose
pin is to be used both for configuration and as a general purpose I/O the user must adhere to the following:
• The general purpose I/O (GPIO) must maintain the same direction as it has during configuration, in other words,
• The I/O type must remain the same, in other words if the pin is a 3.3V CMOS pin (LVCMOS33) during configura-
• The Persistent option must be set to OFF. The Persistent option can be accessed by using the Preference Editor
• The user is responsible for insuring that no internal or external logic will interfere with device configuration.
Also note, if a parallel configuration mode is not being used then one or both of the parallel port chip selects (CSN,
CS1N) must be high or tri-state during configuration.
Programmable options control the dual-purpose configuration pins. These options are controlled via a preference
in Lattice ispLEVER software, or as an HDL source file attribute. The LatticeECP/EC devices also support the
ispJTAG port for configuration, including transparent read back and JTAG testing. The following sections describe
the functionality of the sysCONFIG and JTAG pins. Table 12-1 is provided for reference.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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if the pin is an input during configuration it must remain an input as a GPIO, if an output during configuration it
must remain an output as a GPIO, if a bi-directional it must remain a bi-directional as a GPIO.
tion it must remain a 3.3V CMOS pin as a GPIO.
in ispLEVER
®
.
12-1
LatticeECP/EC sysCONFIG
Usage Guide
Technical Note TN1053
tn1053_02.4