LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 405

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
If the Floorplanner GUI is used, it is strongly recommended that after finding the optimal grouping with the
GUI, grouping attributes (PGROUP and/or UGROUPS) should be inserted into the HDL source code to pre-
serve module performance over design revisions.
Special Floorplanning Considerations
Embedded Block RAM Placement
Block RAM placement can be done with simple LOCATE preferences. It is not always necessary to locate block
RAMs. Do not use the PGROUPs, UGROUPs, or the Floorplanner GUI to group Block RAMs.
I/O Grouping
There is a complete set of physical constraints on PGROUPing I/O components. Please refer to ispLEVER On-line
Help, Defining PIO Component Groups, for keyword explanations and syntax examples.
Large Module Grouping
It is strongly recommended that larger PGROUPs/UGROUPs (with many logical elements) be anchored and
bounded by LOCATE and BBOX keywords. From the STATE_MACHINE example, we see that without anchoring
the groups, the performance worsened compared to no floorplanning at all.
The BBOX should be strategically shaped and sized according to the module to be placed inside the BBOX. If the
BBOX shape and size is not specified, the default BBOX size will be a square that is as small as possible. This is
not the optimal BBOX for typical modules. The designer should shape the design with the datapath in mind and
size the BBOX to be larger then needed so that the ispLEVER placer program can have more flexibility in placing
logic elements inside the BBOX.
Carry Chains and Bus Grouping
Carry chains (used by ripple arithmetic functions like adders, counters, and multipliers) and logic modules con-
nected by busses can easily be floorplanned inappropriately by a designer that is not aware of the internal routing
resources available to optimize these carry chain and bus routes. As we saw from the multiplier example, certain
groupings can reduce the performance of a design compared to no floorplanning at all. Great care should be used
when floorplanning designs that use carry chains or busses so that these routes fall in optimal locations for optimal
performance.
Broken Carry Chain Example
A 9-bit adder that is PGROUPed with no relative placement on the adder. Logic elements such as PFUs may give
worse performance because the adder carry-chain is broken.
SLICs in Groups
For Lattice Semiconductor FPGA device families that contain Supplemental Logic and Interconnect Cells (SLICs),
the SLICs are automatically removed from PGROUPs and UGROUPs by the ispLEVER software if they are not rel-
atively placed. This is because SLICs are used by the tools for interconnects that are not foreseeable by designers.
If SLIC placement has to be controlled for a design, the designer will need to instantiate and locate the SLICS in
their preference or HDL files. It is recommended to allow the ispLEVER software to automatically place SLICs.
Summary
This application note defined floorplanning, discussed when it should be used, and detailed how floorplanning is
done with respect to Lattice Semiconductor FPGA designs. Examples were used to illustrate and compare the dif-
ferent tools available to the designer for floorplanning.
Important items discussed:
• Floorplanning can improve timing for targeted critical paths.
• Improper floorplanning can make timing worse.
16-7
Lattice Semiconductor Design Floorplanning