LFXP3C-4QN208C Lattice, LFXP3C-4QN208C Datasheet - Page 70
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFXP3C-4QN208C
Manufacturer Part Number
LFXP3C-4QN208C
Description
IC FPGA 3.1KLUTS 136I/O 208-PQFP
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP3C-4QN208C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-4QN208C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 70 of 397
- Download datasheet (10Mb)
Lattice Semiconductor
Signal Descriptions (Cont.)
Test and Programming (Dedicated pins. Pull-up is enabled on input pins during configuration.)
TMS
TCK
TDI
TDO
V
Configuration Pads (used during sysCONFIG)
CFG[1:0]
INITN
PROGRAMN
DONE
CCLK
BUSY
CSN
CS1N
WRITEN
D[7:0]
DOUT, CSON
DI
SLEEPN
TOE
1. Applies toþ LFXP10, LFXP15 and LFXP20 only.
2. Applies to LFXP “C” devices only.
3. Applies to LFXP “E” devices only.
CCJ
3
2
Signal Name
I/O
I/O
I/O
I/O Configuration Clock for configuring an FPGA in sysCONFIG mode.
I/O Generally not used. After configuration it is a user-programmable I/O pin.
I/O
—
O
O
I
I
I
I
I
I
I
I
I
I
I
Test Mode Select input, used to control the 1149.1 state machine.
Test Clock input pin, used to clock the 1149.1 state machine.
Test Data in pin, used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence).
Output pin -Test Data out pin used to shift data out of device using 1149.1.
V
Mode pins used to specify configuration modes values latched on rising edge
of INITN. During configuration, a pull-up is enabled.
Open Drain pin - Indicates the FPGA is ready to be configured. During con-
figuration, a pull-up is enabled. If CFG1 and CFG0 are high (SDM) then this
pin is pulled low.
Initiates configuration sequence when asserted low. This pin always has an
active pull-up.
Open Drain pin - Indicates that the configuration sequence is complete, and
the startup sequence is in progress.
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled. After configuration it is user a programmable I/O pin.
sysCONFIG chip select (Active Low). During configuration, a pull-up is
enabled. After configuration it is user programmable I/O pin
Write Data on Parallel port (Active low). After configuration it is a user pro-
grammable I/O pin
sysCONFIG Port Data I/O. After configuration these are user programmable
I/O pins.
Output for serial configuration data (rising edge of CCLK) when using sys-
CONFIG port. After configuration, it is a user-programmable I/O pin.
Input for serial configuration data (clocked with CCLK) when using sysCON-
FIG port. During configuration, a pull-up is enabled. After configuration it is a
user-programmable I/O pin.
Sleep Mode pin - Active low sleep pin.þ When this pin is held high, the device
operates normally.þ When driven low, the device moves into Sleep Mode
after a specified time.This pin has a weak internal pull-up, but when not used
an external pull-up to V
Test Output Enable tri-states all I/O pins when driven low. This pin has a
weak internal pull-up, but when not used an external pull-up to V
mended.
CCJ
- The power supply pin for JTAG Test Access Port.
4-2
CC
is recommended.
Descriptions
LatticeXP Family Data Sheet
Pinout Information
CC
is recom-
Related parts for LFXP3C-4QN208C
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![LFXP3C-4TN144C](/photos/16/14/161488/tqfp-144_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V -4 Spd
Manufacturer:
Lattice
Datasheet:
![LFXP3C-4TN100C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 3.1K LUTs 62 I/O 1.8/2.5/3.3V -4 Spd
Manufacturer:
Lattice
Datasheet:
![LFXP3C-4Q208C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 3.1K LUTs 136 IO 1.8 /2.5/3.3V -4 Spd
Manufacturer:
Lattice
![LFXP3C-4T144I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 3.1K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer:
Lattice
![LFXP3C-4Q208I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 3.1K LUTs 136 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer:
Lattice
![LFXP3C-3TN144C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 3.1K LUTS 100 I/O
Manufacturer:
Lattice
Datasheet:
![LFXP3C-3QN208C](/photos/16/15/161504/qfp208_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 3.1K LUTS 136 I/O
Manufacturer:
Lattice
Datasheet:
![LFXP3C-3TN100C](/photos/16/2/160258/tqfp-100_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 3.1K LUTS 62 I/O
Manufacturer:
Lattice
Datasheet:
![LFXP3C-5TN100C](/photos/16/2/160258/tqfp-100_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 3.1K LUTS 62 I/O
Manufacturer:
Lattice
Datasheet:
![LFXP3C-3TN100I](/photos/16/2/160258/tqfp-100_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
Manufacturer:
Lattice
Datasheet:
![LFXP3C-3TN144I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
Manufacturer:
Lattice
Datasheet:
![LFXP3C-5TN144C](/photos/19/4/190401/ge144tqfp05-40_tmb.jpg)
Part Number:
Description:
FPGA, 1.8V FLASH, INSTANT ON, SMD
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFXP3C-3QN208I](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
FPGA LatticeXP Family 3000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFXP3C-3T144I](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
FPGA LatticeXP Family 3000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 144-Pin TQFP Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFXP3C-4T100I](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
FPGA LatticeXP Family 3000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 100-Pin TQFP Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet: