LFXP6C-3TN144I Lattice, LFXP6C-3TN144I Datasheet - Page 230
LFXP6C-3TN144I
Manufacturer Part Number
LFXP6C-3TN144I
Description
IC FPGA 5.8KLUTS 100I/O 144-TQFP
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP6C-3TN144I
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Part Number:
LFXP6C-3TN144I
Manufacturer:
Lattice Semiconductor Corporation
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Figure 10-12. READ Data Transfer When DDRCLKPOL=0
DDRCLKPOL= 0
IO REGISTERS
Notes -
CLK TO SYNC
(1) DDR memory sends DQ aligned to DQS strobe.
(2) The DQS Strobe is delayed by 90 degree using the dedicated DQS logic.
(3) DQ is now center aligned to DQS Strobe.
(4) PRMBDET is the Preamble detect signal generated using the DQSBUFB primitive. This is used to
(5) The first set of IO registers A and B, capture data on the positive edge and negative edge of DQS.
(6) IO register C transfers data so that both data are now aligned to negative edge of DQS.
(7) DDCLKPOL signal generated will determine if the CLK going into the synchronization registers need to
(8) The IO Synchronization registers capture data at on positive edge of the FPGA CLK.
DQS at PIN
DQS at IOL
FPGA CLK
PRMBDET
generate the DDRCLKPOL signal.
be inverted. In this case, the DDRCLKPOL=0 as the CLK is LOW at the 1
DATAIN_P
DATAIN_N
DQ at PIN
DQ at IOL
C
A
B
P0
P0
10-11
N0
N0
P0
P1
P1
N0
P0
N1
P1
N1
P0
N0
N1
P1
st
LatticeECP/EC and LatticeXP
rising edge of PRMBDET.
DDR Usage Guide
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