LFE2-12E-7FN256C Lattice, LFE2-12E-7FN256C Datasheet - Page 62
LFE2-12E-7FN256C
Manufacturer Part Number
LFE2-12E-7FN256C
Description
IC FPGA 12KLUTS 193I/O 256-BGA
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-12E-7FN256C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Lattice Semiconductor
sysI/O Differential Electrical Characteristics
LVDS
Differential HSTL and SSTL
Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-
able single-ended output classes (class I and class II) are supported in this mode.
For further information about LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see the list
of additional technical information at the end of this data sheet.
V
V
V
I
V
V
V
ΔV
V
ΔV
I
I
Parameter
IN
SA
SAB
OH
OL
OD
OS
INP
CM
THD
OD
OS
, V
INM
Input Voltage
Input Common Mode Voltage
Differential Input Threshold
Input Current
Output High Voltage for V
Output Low Voltage for V
Output Voltage Differential
Change in V
Low
Output Voltage Offset
Change in V
Output Short Circuit Current
Output Short Circuit Current
Description
OD
OS
Between High and
Between H and L
Over Recommended Operating Conditions
OP
OP
or V
or V
OM
OM
Half the Sum of the Two Inputs
Difference Between the Two Inputs
Power On or Power Off
R
R
(V
(V
V
Ground
V
Each Other
OD
OD
T
T
OP
OP
= 100 Ohm
= 100 Ohm
= 0V Driver Outputs Shorted to
= 0V Driver Outputs Shorted to
- V
+ V
OM
OM
3-11
Test Conditions
), R
)/2, R
T
= 100 Ohm
T
= 100 Ohm
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
+/-100
1.125
0.9V
Min.
0.05
250
—
—
—
—
—
—
0
Typ.
1.38
1.03
1.20
350
—
—
—
—
—
—
—
—
1.375
Max.
+/-10
1.60
2.35
450
2.4
50
50
24
12
—
—
Units
mV
mV
mV
mV
mA
mA
µA
V
V
V
V
V
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