DG409DVZ Intersil, DG409DVZ Datasheet - Page 8
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DG409DVZ
Manufacturer Part Number
DG409DVZ
Description
IC MULTIPLEXER DUAL 4X1 16TSSOP
Manufacturer
Intersil
Type
Analog Multiplexerr
Datasheet
1.DG408DJZ.pdf
(17 pages)
Specifications of DG409DVZ
Function
Multiplexer
Circuit
2 x 4:1
On-state Resistance
100 Ohm
Voltage Supply Source
Single, Dual Supply
Voltage - Supply, Single/dual (±)
5 V ~ 34 V, ±5 V ~ 20 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Package
16TSSOP
Maximum On Resistance
100@±15V Ohm
Maximum Propagation Delay Bus To Bus
250@±15V@-40C to 85C|180(Typ)@12V ns
Maximum High Level Output Current
30 mA
Multiplexer Architecture
4:1
Maximum Turn-off Time
120(Typ)@12V ns
Maximum Turn-on Time
180(Typ)@12V ns
Power Supply Type
Single|Dual
Rohs Compliant
YES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DG409DVZ
Manufacturer:
Intersil
Quantity:
384
Company:
Part Number:
DG409DVZ
Manufacturer:
Intersil
Quantity:
416
Part Number:
DG409DVZ
Manufacturer:
VISHAY/威世
Quantity:
20 000
Part Number:
DG409DVZ-T
Manufacturer:
INTERSIL
Quantity:
20 000
Test Circuits and Waveforms
Typical Applications
Overvoltage Protection
A very convenient form of overvoltage protection consists of
adding two small signal diodes (1N4148, 1N914 type) in
series with the supply pins (see Figure 9). This arrangement
effectively blocks the flow of reverse currents. It also floats
the supply pin above or below the normal V+ or V- value. In
this case the overvoltage signal actually becomes the power
supply of the IC. From the point of view of the chip, nothing
has changed, as long as the difference V+ - (V-) doesn’t
exceed 44V. The addition of these diodes will reduce the
analog signal range to 1V below V+ and 1V above V-, but it
preserves the low channel resistance and low leakage
characteristics.
Typical application information is for Design Aid Only, not
guaranteed and not subject to production testing.
GENERATOR
ANALYZER
SIGNAL
INSERTION LOSS
FIGURE 7. INSERTION LOSS
V
IN
A
A
A
S
1
2
1
0
GND
8
EN
=
5V
20 Log
+15V
-
15V
V+
V
-
V
-----------------
D
V
OUT
IN
(Continued)
R
L
V
DG408, DG409
O
CHANNEL
FIGURE 9. OVERVOLTAGE PROTECTION USING BLOCKING
SELECT
FIGURE 8. SOURCE/DRAIN CAPACITANCES
V
G
DIODES
3V OR 0V
A
A
A
2
1
0
EN
S
GND
X
+15V
-
15V
V+
V
-
S
S
V+
V
D
|
|
1
8
-
DG408
1N4148
1N4148
D
IMPEDANCE
ANALYZER
June 13, 2006
FN3283.8