MT48LC16M16A2P-75:DTR Micron Technology Inc, MT48LC16M16A2P-75:DTR Datasheet - Page 69
MT48LC16M16A2P-75:DTR
Manufacturer Part Number
MT48LC16M16A2P-75:DTR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC16M16A2P-75DTR.pdf
(87 pages)
Specifications of MT48LC16M16A2P-75:DTR
Lead Free Status / Rohs Status
Compliant
- Current page: 69 of 87
- Download datasheet (4Mb)
Figure 39: READ With Auto Precharge Interrupted by a READ
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Internal
states
Command
Note:
Address
Bank m
Bank n
CLK
DQ
registered. The last valid data WRITE to bank n will be data registered one clock prior to
a WRITE to bank m (see Figure 46 (page 75)).
1. DQM is LOW.
Page active
NOP
T0
READ - AP
Page active
Bank n,
Bank n
T1
Col a
READ with burst of 4
T2
CL = 3 (bank n)
NOP
69
READ - AP
Bank m,
T3
Bank m
Col d
Interrupt burst, precharge
READ with burst of 4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T4
CL = 3 (bank m)
NOP
t
RP - bank n
D
OUT
T5
NOP
256Mb: x4, x8, x16 SDRAM
D
OUT
PRECHARGE Operation
T6
NOP
D
© 1999 Micron Technology, Inc. All rights reserved.
OUT
Idle
T7
Don’t Care
NOP
t RP - bank m
D
Precharge
OUT
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