MT48LC4M16A2P-75:GTR Micron Technology Inc, MT48LC4M16A2P-75:GTR Datasheet - Page 58
MT48LC4M16A2P-75:GTR
Manufacturer Part Number
MT48LC4M16A2P-75:GTR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC4M16A2P-75GTR.pdf
(72 pages)
Specifications of MT48LC4M16A2P-75:GTR
Lead Free Status / Rohs Status
Compliant
- Current page: 58 of 72
- Download datasheet (4Mb)
Figure 41:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
DQML, DQMH
A0–A9, A11
COMMAND
BA0, BA1
DQM /
CLK
CKE
A10
DQ
t CKS
t CMS
READ – With Auto Precharge
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
t CMH
t CKH
Notes:
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
T1
1. For this example, BL = 4, and CL = 2.
2. x16: A8, A9 and A11 = “Don’t Care”
NOP
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
ENABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
BANK
T2
READ
t CMH
t CH
CAS Latency
T3
NOP
t LZ
t AC
58
T4
D
NOP
OUT
t OH
t AC
m
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
OUT
T5
NOP
m + 1
t OH
t AC
D
OUT
T6
NOP
64Mb: x4, x8, x16 SDRAM
m + 2
t OH
t AC
t RP
©2000 Micron Technology, Inc. All rights reserved.
D
OUT
T7
NOP
Timing Diagrams
m + 3
t OH
t HZ
T8
BANK
ACTIVE
ROW
ROW
DON’T CARE
UNDEFINED
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