SAK-C167CS-L33M Infineon Technologies, SAK-C167CS-L33M Datasheet - Page 38

• Manufacturer Part Number: SAK-C167CS-L33M
• Manufacturer: Infineon Technologies

Specifications of SAK-C167CS-L33M

• Cpu Family: C166
• Device Core Size: 16b
• Frequency (max): 33MHz
• Interface Type: CAN/SPI/USART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 11KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 24-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: MQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock/OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.
In direct drive mode the PLL base frequency is used directly (
In prescaler mode the PLL base frequency is divided by 2 (
Note: The CPU clock source is only switched back to the oscillator clock after a
The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.
In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the
CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also
no interrupt request will be generated in case of a missing oscillator clock.
Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD at that time.
Data Sheet
hardware reset.
Thus the oscillator watchdog may also be disabled via hardware by (externally)
pulling the RD line low upon a reset, similar to the standard reset configuration via
PORT0.
34
f
CPU
f
CPU
= 1 … 2.5 MHz).
= 2 … 5 MHz).
C167CS-4R
V2.2, 2001-08
C167CS-L