PCF8562TT NXP Semiconductors, PCF8562TT Datasheet - Page 20

• Manufacturer Part Number: PCF8562TT
• Manufacturer: NXP Semiconductors

Specifications of PCF8562TT

• Operating Supply Voltage (typ): 2.5/3.3/5V
• Number Of Digits: 16
• Number Of Segments: 128
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Pin Count: 48
• Mounting: Surface Mount
• Power Dissipation: 400mW
• Frequency (max): 400KHz
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
PCF8562_2
Product data sheet
7.4 Acknowledge
7.5 PCF8562 I
7.6 Input filters
The number of data bytes that can be transferred from transmitter to receiver between the
Start and Stop conditions is unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH-level signal on the bus that is asserted
by the transmitter during which time the master generates an extra acknowledge related
clock pulse. An addressed slave receiver must generate an acknowledge after receiving
each byte. Also a master receiver must generate an acknowledge after receiving each
byte that has been clocked out of the slave transmitter. The acknowledging device must
pull-down the SDA line during the acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold
times must be taken into consideration). A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave. In this event the transmitter must leave the data line HIGH to enable the
master to generate a Stop condition (see
The PCF8562 acts as an I
transmit data to an I
the acknowledge signals of the selected devices. Device selection depends on the
I
subaddress.
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
2
Fig 14. Acknowledgement on the I
C-bus slave address, on the transferred command data and on the hardware
by transmitter
data output
by receiver
data output
SCL from
master
2
C-bus controller
2
condition
START
C-bus master receiver. The only data output from the PCF8562 are
Rev. 02 — 22 January 2007
S
2
C-bus slave receiver. It does not initiate I
2
1
C-bus
Figure
Universal LCD driver for low multiplex rates
2
14).
not acknowledge
acknowledge
8
2
acknowledgement
C-bus transfers or
clock pulse for
PCF8562
© NXP B.V. 2007. All rights reserved.
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