MT48LC8M32B2B5-6 Micron Technology Inc, MT48LC8M32B2B5-6 Datasheet - Page 24

• Manufacturer Part Number: MT48LC8M32B2B5-6
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M32B2B5-6

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

NOTE:
NOTE:
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
COMMAND
COMMAND
t
t
WR = 1 CLK (
WR = 2 CLK (when
Figure 22: Terminating a WRITE Burst
ADDRESS
ADDRESS
DQM could remain LOW in this example if the WRITE
burst is a fixed length of two.
DQM is LOW.
DQM
DQM
CLK
Figure 21: WRITE to PRECHARGE
DQ
DQ
t
CK >
BANK a,
BANK a,
WRITE
WRITE
COL n
COL n
D
D
T0
COMMAND
n
n
IN
IN
t
t
ADDRESS
WR)
WR >
CLK
t
n + 1
n + 1
NOP
CK)
NOP
DQ
T1
D
D
IN
IN
t
WR
PRECHARGE
BANK,
(a or all)
WRITE
COL n
BANK
NOP
D
T2
T0
n
IN
t
WR
PRECHARGE
TERMINATE
(a or all)
BANK
T3
NOP
BURST
T1
t RP
DON’T CARE
NOP
NOP
COMMAND
(ADDRESS)
T4
(DATA)
NEXT
T2
t RP
BANK a,
ACTIVE
ROW
NOP
T5
DON’T CARE
BANK a,
ACTIVE
ROW
NOP
T6
24
PRECHARGE
The PRECHARGE command (Figure 23) is used to
deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (
after the PRECHARGE command is issued. Input A10
determines whether one or all banks are to be pre-
charged, and in the case where only one bank is to be
precharged, inputs BA0 and BA1 select the bank. When
all banks are to be precharged, inputs BA0 and BA1 are
treated as “Don’t Care.” Once a bank has been pre-
charged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank.
POWER-DOWN
Power-down occurs if CKE is registered LOW coinci-
dent with a NOP or COMMAND INHIBIT when no
accesses are in progress (see Figure 24). If power-down
occurs when all banks are idle, this mode is referred to
as precharge power-down; if power-down occurs when
there is a row active in either bank, this mode is
referred to as active power-down. Entering power-
down deactivates the input and output buffers, exclud-
ing CKE, for maximum power savings while in standby.
The device may not remain in the power-down state
longer than the refresh period (64ms) since no
REFRESH operations are performed in this mode.
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting
Figure 23: PRECHARGE Command
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A0-A9, A11
BA0, BA1
RAS#
CAS#
WE#
CKE
CLK
A10
CS#
HIGH
t
CKS).
VALID ADDRESS
©2003 Micron Technology, Inc. All rights reserved.
Bank Selected
All Banks
ADDRESS
BANK
256Mb: x32
DON’T CARE
SDRAM
t
RP)