ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 112

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
DDC STATUS REGISTER 2 (SR2)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 = AF Acknowledge failure .
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
Bit 3 = STOPF Stop detection.
This bit is set by hardware when a Stop condition is
detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
Bit 2 = Reserved. Forced to 0 by hardware.
112/144
0: No acknowledge failure
1: Acknowledge failure
0: No Stop condition detected
1: Stop condition detected
7
0
0
0
AF
STOPF
0
BERR
EDDC
0
F
Bit 1 = BERR Bus error.
This bit is set by hardware when the interface
detects a misplaced Start or Stop condition. An
interrupt is generated if ITE=1. It is cleared by
software reading SR2 register or by hardware
when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
Bit 0 = EDDCF Enhanced DDC address detected.
This bit is set by hardware when the Enhanced
DDC address (60h/61h) is detected on the bus
while EDDCEN=1. It is cleared by hardware when
a Start or a Stop condition (STOPF=1) is detected,
or when the interface is disabled (PE=0).
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
0: No Enhanced DDC address detected on bus
1: Enhanced DDC address detected on bus