CY26049ZC-36 Cypress Semiconductor Corp, CY26049ZC-36 Datasheet - Page 5

• Manufacturer Part Number: CY26049ZC-36
• Manufacturer: Cypress Semiconductor Corp
• Type: PLL Frequency Synthesizerr

Specifications of CY26049ZC-36

• Number Of Elements: 1
• Supply Current: 45mA
• Pll Input Freq (min): 10/0.008(Typ)MHz
• Pll Input Freq (max): 60MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Output Frequency Range: 0.008 to 155.52MHz
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temperature Classification: Commercial
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

DC Electrical Specifications
AC Electrical Specifications
Voltage and Timing Definitions
Notes
Document #: 38-07415 Rev. *E
I
I
V
V
I
I
C
I
I
f
f
LR
t
t
t
t
t
f
ER
EF
Parameter
3. Dependent on crystals chosen and crystal specs.
4. Lock times are measured beginning when VDD has reached its minimum specified value and ICLK is stable.
OH
OL
IH
IL
OZ
DD
ICLK-E
ICLK-B
DC
PJIT1
PJIT2
P_LOCK
FS_LOCK
ERROR
Parameter
IH
IL
IN
= t
2
/t
1
Frequency, Input Clock
Frequency, Input Clock
FailSafe Lock Range
Output Duty Cycle
Clock Jitter; output > 5 MHz Period Jitter, Peak to Peak, 10,000 periods
Clock Jitter; output < 5 MHz Period Jitter, Peak to Peak, 10,000 periods
PLL Lock Time
Failsafe Lock Time
Frequency Synthesis Error
Rising Edge Rate
Falling Edge Rate
Output High Current
Output Low Current
Input High Voltage
Input High Voltage
Input High Current
Input Low Current
Input Capacitance
Output Leakage Current
Supply Current
Description
Description
Figure 3. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
[4]
[4]
[3]
CLK
(Industrial Temp: –40° to 85°C)
(Commercial Temp: 0° to 70° C and Industrial Temp: –40° to 85°C)
Figure 2. Duty Cycle Definition; DC = t2/t1
V
V
CMOS Levels
CMOS Levels
V
V
High Z
C
C
Input Clock Frequency, External Mode
Input Clock Frequency, Buffer Mode
Range of reference ICLK for Safe = High
Duty Cycle defined in
RMS Period Jitter, RMS
RMS Period Jitter, RMS
Time for PLL to lock within ± 150 ppm of target frequency
Time for PLL to lock to ICKL (outputs phase aligned with
ICKL and Safe = High)
Actual mean frequency error versus target
Output Clock Edge Rate, Measured from 20% to 80% of
V
Output Clock Edge Rate, Measured from 20% to 80% of
V
OH
OL
IH
IL
LOAD
LOAD
DD
DD
CLK
= 0V
= V
, C
, C
= 0.5, V
= V
[1]
= 15 pF, V
= 15 pF, V
LOAD
LOAD
DD
DD
output
50%
– 0.5, V
t1
t2
DD
= 15 pF See
= 15 pF See
t3
= 3.3V (sink)
DD
DD
Test Conditions
DD
Test Conditions
= 3.45V, FS [3:0] = 0100
= 3.45V, FS [3:0] = 1101
Figure
80%
20%
= 3.3V (source)
50%
Figure
Figure
2, measured at 50% of V
t4
3.
3.
DD
Min
0.7
10
10
–250
–
–
–
–
–
–
–
Min
0.8
0.8
10
45
–
–
–
–
–
–
–
–
Typ
± 5
20
20
8.00
–
–
5
5
–
–
–
Typ
1.4
1.4
50
–
–
–
–
–
–
–
–
0
CY26049-36
Max
0.3
10
10
50
35
+250 ppm
Max
–
–
–
7
–
250
500
100
60
55
50
–
3
7
–
2
2
Page 5 of 8
Unit
V
V
mA
mA
mA
mA
μA
μA
pF
μA
MHz
ppm
V/ns
V/ns
Unit
kHz
DD
DD
ms
ps
ps
ps
ps
%
s
[+] Feedback