N28F001BXT150 Intel, N28F001BXT150 Datasheet - Page 15

• Manufacturer Part Number: N28F001BXT150
• Manufacturer: Intel

Specifications of N28F001BXT150

• Density: 1Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 17b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 128K
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

4.3
The 28F001BX contains a status register which
may be read to determine when a program or erase
operation is complete, and whether that operation
completed successfully. The status register may be
read at any time by writing the Read Status
Register command (70H) to the command register.
After writing this command, all subsequent read
operations output data from the status register, until
another valid command is written to the command
register. The contents of the status register are
latched on the falling edge of OE# or CE#,
whichever occurs last in the read cycle. OE# or
CE# must be toggled to V
update the status register latch. The Read Status
Register command functions when V
V
4.4
The erase status and program status bits are set to
“1” by the Write State Machine and can only be
reset by the Clear Status Register command.
These bits indicate various failure conditions (see
Table 4). By allowing system software to control the
resetting of these bits, several operations may be
performed (such as cumulatively programming
several bytes or erasing multiple blocks in
sequence). The status register may then be polled
to determine if an error occurred during that series.
This adds flexibility to the way the device may be
used.
Additionally, the V
“1,” must be reset by system software before
further
attempted. To clear the status register, the Clear
Status Register command (50H) is written to the
command register. The Clear Status Register
command is functional when V
PPH
.
byte
Read Status Register
Command
Clear Status Register
Command
programs
PP
status bit (SR.3), when set to
IH
or
before further reads to
PP
block
= V
PPL
PP
erases
or V
= V
PPH
PPL
.
are
or
4.5
Erase is executed one block at a time, initiated by a
two-cycle command sequence. An Erase Setup
command (20H) is first written to the command
register, followed by the Erase Confirm command
(D0H). These commands require both appropriate
command data and an address within the block to
be erased. Block preconditioning, erase and verify
are all handled internally by the Write State
Machine, invisible to the system. After receiving the
two-command erase sequence, the 28F001BX
automatically outputs status register data when
read (see Figure 9, 28F001BX Block Erase
Flowchart ). The CPU can detect the completion of
the erase event by checking the WSM status bit of
the status register (SR.7).
When the status register indicates that erase is
complete, the erase status bit should be checked. If
erase error is detected, the status register should
be cleared. The command register remains in read
status register mode until further commands are
issued to it.
This two-step sequence of set-up followed by
execution ensures that memory contents are not
accidentally erased. Also, block erasure can only
occur when V
voltage, memory contents are protected against
erasure. If block erase is attempted while V
V
attempts while V
results and should not be attempted.
4.6
The Erase Suspend command allows erase
sequence interruption in order to read data from
another block of memory. Once the erase sequence
is started, writing the Erase Suspend command
(B0H) to the command register requests that the
WSM
predetermined point in the erase algorithm. The
28F001BX continues to output status register data
when read, after the Erase Suspend command is
written to it. Polling the WSM status and erase
suspend status bits will determine when the erase
operation has been suspended (both will be set to
“1s”).
PPL
, the V
suspend
Erase Setup/Erase Confirm
Commands
Erase Suspend/Erase Resume
Commands
PP
PP
status bit will be set to “1”. Erase
= V
PPL
the
PPH
< V
. In the absence of this high
PP
erase
< V
PPH
sequence
produce spurious
28F001BX
at
PP
15
=
a