M69030 Asiliant Technologies, M69030 Datasheet - Page 166
M69030
Manufacturer Part Number
M69030
Description
Manufacturer
Asiliant Technologies
Datasheet
1.M69030.pdf
(387 pages)
Specifications of M69030
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M69030
Manufacturer:
CHIPS
Quantity:
20 000
Part Number:
M69030P
Manufacturer:
MIT
Quantity:
20 000
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11-10
GR07
read/write at I/O address 3CFh with index at address 3CEh set to 07h
shared by both pipelines A and B
7-4
3-0
GR08
read/write at I/O address 3CFh with index at address 3CEh set to 08h
shared by both pipelines A and B
7-0
`efmp
A
&
B
A
&
B
Reserved
Ignore Color Plane 3 through Ignore Color Plane 0
Bit Mask
69030 Databook
7
7
Color Don’t Care Register
Bit Mask Register
0: The corresponding bit in the Color Compare Register (GR02) will not be included in color
comparisons.
1: The corresponding bit in the Color Compare Register (GR02) is used in color
comparisons.
Note: These bits have effect only when bit 3 of the Graphics Mode Register (GR05) is set
to 1 to select read mode 1.
0: The corresponding bit in each of the 4 memory planes is written to with the
corresponding bit in the memory read latches.
1: Manipulation of the corresponding bit in each of the 4 memory planes via other
mechanisms is enabled.
Note: This bit mask applies to any writes to the addressed byte of any or all of the 4
memory planes simultaneously.
Note: This bit mask is applicable to any data written into the frame buffer by the CPU,
including data that is also subject to rotation, logical functions (AND, OR, XOR), and Set/
Reset. To perform a proper read-modify-write cycle into the frame buffer, each byte must
first be read from the frame buffer by the CPU (and this will cause it to be stored in the
memory read latches), this Bit Mask Register must be set and the new data then written
into the frame buffer by the CPU.
6
6
Reserved
5
5
Graphics Controller Registers
4
4
Bit Mask
Plane 3
Ignore
Color
3
3
Plane 2
Ignore
Color
2
2
Plane 1
Ignore
Revision 1.3 11/24/99
Color
1
1
Plane 0
Ignore
Color
0
0
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