M69030 Asiliant Technologies, M69030 Datasheet - Page 260

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

15-22
FR13
read/write at I/O address 3D1h with index at I/O address 3D0h set to 13h
shadowed only for pipeline A
7-3
2
1-0
`efmp
A
B

Reserved (R/W) (reset state: 0000-0)
Increase Setup Time 16-bit Color STN-DD
Color STN Pixel Packing
69030 Databook
7
FP Format 3 Register
0: Normal data setup time with respect to SHFCLK falling edge (default). Maximum
SHFCLK frequency is DCLK/2 (1:1 duty cycle).
1: Extended data setup time with respect to SHFCLK falling edge. The setup time is
increased by approximately half of a dot clock cycle. This is done by extending SHFCLK
high time by half of a dot clock cycle. Maximum SHFCLK frequency is DCLK/2.5 with a
1.5:1 duty cycle.
This bit is effective only for 16-bit Color STN-DD when frame acceleration is enabled or for
8-bit Color STN-DD when frame acceleration is disabled.
This determines the type of pixel packing (the RGB pixel output sequence) for color STN
panels. These bits must be programmed to 00 for monochrome STN panels and for all TFT
panels.
Bits
1 0
0 0
0 1
1 0
1 1
6
3-bit pack (default).
4-bit pack.
Reserved.
Extended 4-bit pack. Bits FR10 Bits 6-4 must be programmed
Reserved (R/W)
to 001. This setting may only be used for 8-bit interface color
STN SS panels.
(0000:0)
5
not shadowed for this pipeline
Flat Panel Registers
Color STN Pixel Packing
4
3
Set Up Time
(0)
2
Revision 1.3 11/24/99
1
Pixel Packing
(00)
0