M69030 Asiliant Technologies, M69030 Datasheet - Page 273
M69030
Manufacturer Part Number
M69030
Description
Manufacturer
Asiliant Technologies
Datasheet
1.M69030.pdf
(387 pages)
Specifications of M69030
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Quantity
Price
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Manufacturer:
CHIPS
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M69030P
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MIT
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FR36
read/write at I/O address 3D1h with index at I/O address 3D0h set to 36h
shadowed only for pipeline A
7-4
3-0
FR37
read/write at I/O address 3D1h with index at I/O address 3D0h set to 37h
shadowed only for pipeline A
Note: When the FP Display engine is enabled (FR01 bit one is set to 1) it uses this register.
7
6
5-3
2-0
`efmp
A
V
A
B
FLM Delay
FP FLM Delay Bits 11-8
FP Vertical Total MSB
FP VSync (FLM) Delay Disable
FP VSync (FLM) select
FP Vsync (FLM) width.
Reserved
69030 Databook
7
7
FP Vertical Overflow 2 Register
FP VSync (FLM) Disable Register
See description of FR34.
See description of FR33.
This bit is effective when FR37 bit 6 is set to 0.
0: FP VSync (FLM) delay enable
1: FP VSync (FLM) delay disable
0: FP VSync (FLM) is generated using FR37 bit 7 and FP VSync (FLM) Delay (FR36 bits
6-4 and FR34) .
1: FP VSync (FLM) is the same as CRT VSync. FR37 bit 7 is ignored in this case.
These bits are effective only if bit 6 is 0.
These bits should always be written to with a value of zero.
FLM Select
FP FLM Delay MSB
6
6
5
5
FP VSync (FLM) width
not shadowed for this pipeline
not shadowed for this pipeline
Flat Panel Registers
Programmed value = actual value -1
4
4
3
3
FP Vertical Total MSB
2
2
Reserved (000)
Revision 1.3 11/24/99
1
1
0
0
15-35
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