M69030 Asiliant Technologies, M69030 Datasheet - Page 344

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

B-4
Programming Constraints
The programmer must be aware of the following five programming constraints:
The constraints have to do with trade-offs between optimum speed with lowest noise, VCO stability and
factors affecting the loop equation.
The value of F
below 100 MHz, F
To avoid crosstalk between the VCOs, the VCO frequencies should not be within 0.5% of each other nor
should their harmonics be within 0.5% of the other’s fundamental frequency.
The graphics controller’s clock synthesizers will seek the new frequency as soon as it is loaded following a
write to the control register. Any change in the post-divisor will take affect immediately. There is also the
consideration of changing from a low frequency VCO value with a post-divide÷1 (e.g., 100 MHz) to a high
frequency ÷ 4 (e.g., 220 MHz). Although the beginning and ending frequencies are close together, the
intermediate frequencies may cause the graphics controller to fail in some environments. In this example,
there will be a short-lived time during which the output frequency will be approximately 12.5 MHz. The
graphics controller provides the mux for MCLK so it can select the fixed frequency (25.175 MHz) before
programming a new frequency. Because of this, the bus interface may not function correctly if the MCLK
frequency falls below a certain value. Register and memory accesses synchronized to MCLK may be too
slow and violate the bus timing causing a watchdog timer error.
Programming Example
The following is an example of the calculations which are performed.
Derive the proper programming word for a 25.175 MHz output frequency using a 14.31818 MHz reference
frequency.
The result:
Several choices for M and N are available:
Choose (M, N) = (211, 30) for best accuracy.
Therefore M is less than 255 and VLD = 1, P = 4.
`efmp

69030 Databook
VCO
1 MHz ≤ F
150 KHz ≤ F
100 MHz ≤ F
3 ≤ M ≤ 257
3 ≤ N ≤ 257
Since 25.175 MHz < 100 MHz, quadruple it to 100.70 MHz to get F
Set the post divide (PD) divide by 4.
Video Loop Divisor Selector (VLD) = 1
F
M/N = 7.0330
VCO
VCO
must remain between 100 MHz and 220 MHz inclusive. Therefore, for output frequencies
= 100.70 = (14.31818 x M/N)
must be brought into range by using the post-VCO Divisor.
REF
REF
VCO
≤ 83 MHz
/(N) ≤ 5 MHz
≤ 220 MHz
211
204
M
30
29
N
Clock Generation
100.70
100.72
F
VCO
+0.00021
-0.00005
Error
VCO
Revision 1.3 11/24/99
in its valid range.