M69030 Asiliant Technologies, M69030 Datasheet - Page 8

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

vi
Chapter 5
I/O and Memory Address Maps
Chapter 6
Register Summaries
Chapter 7
PCI Configuration Registers
Chapter 8
General Control and Status Registers
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Introduction .................................................................................................................................. 5-1
VGA-Compatible Address Map ................................................................................................... 5-1
Address Maps for Going Beyond VGA ........................................................................................ 5-2
Lower Memory Map ..................................................................................................................... 5-2
I/O and Sub-Addressed Register Map ........................................................................................ 5-2
Sub-Indexing Indices and Data Ports .......................................................................................... 5-4
Register Shadowing Schemes for Dual-Pipe .............................................................................. 5-5
I/O Space Register Shadowing ................................................................................................... 5-5
Memory Space Register Shadowing ........................................................................................... 5-7
Video Playback Engine Register Cross-Sharing ......................................................................... 5-7
Two-Way Sub-Indexed Register Indices ..................................................................................... 5-9
Upper Memory Map -- Dual-Pipe Mapping ................................................................................ 5-10
Upper Memory Map -- Multiple-Endian Mapping ....................................................................... 5-10
Introduction .................................................................................................................................. 6-1
Introduction .................................................................................................................................. 7-1
VENDIDD
DEVID
DEVCTL
DEVSTAT
REV
PRG
SUB
BASE
HDR
MBASE
SUBVENDID
SUBDEVDID
INTLINE
INTPIN
RBASE
SUBVENDSET
SUBDEVSET
Introduction .................................................................................................................................. 8-1
ST00
ST01
FCR
MSR
IOSS
MSS

69030 Databook
Vendor ID Register ......................................................................................... 7-2
Device ID Register ......................................................................................... 7-2
Device Control Register ................................................................................. 7-3
Device Status Register ................................................................................... 7-5
Revision ID Register ...................................................................................... 7-7
Register-Level Programming Interface Register ............................................ 7-7
Sub-Class Code Register ............................................................................... 7-8
Base Class Code Register ............................................................................. 7-8
Header Type Register .................................................................................... 7-9
Memory Base Address Register .................................................................. 7-10
Subsystem Vendor ID Register .................................................................... 7-11
Subsystem Device ID Register .................................................................... 7-11
Interrupt Line Register .................................................................................. 7-12
Interrupt Pin Register ................................................................................... 7-12
ROM Base Address Register ....................................................................... 7-13
Subsystem Vendor ID Set Register ............................................................. 7-14
Subsystem Device ID Set ............................................................................ 7-14
Input Status Register 0 ................................................................................... 8-2
Input Status Register 1 ................................................................................... 8-3
Feature Control Register ................................................................................ 8-4
Miscellaneous Output Register ...................................................................... 8-5
I/O Space Shadowing Register ...................................................................... 8-7
Memory Space Shadowing Register ............................................................ 8-13
Revision 1.3 11/24/99