MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 203
MC9S12C128VFU
Manufacturer Part Number
MC9S12C128VFU
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12C128VFU.pdf
(690 pages)
Specifications of MC9S12C128VFU
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/SCI/SPI
Program Memory Type
Flash
Program Memory Size
128KB
Total Internal Ram Size
4KB
# I/os (max)
60
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/2.97V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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7.3.2.5
1. See
2. Current HCS12 implementations have PPAGE limited to 6 bits. Therefore, EXTCMP[5:4] should be set to 00.
3. Data page (DPAGE) and Extra page (EPAGE) are reserved for implementation on devices that support paged data and extra
Freescale Semiconductor
Module Base + 0x0025
Starting address location affected by INITRG register setting.
EXTCMP
space.
PAGSEL
PAGSEL
Reset
Field
10
11
7:6
5:0
00
01
Figure
W
(3)
R
2
7-10.
Page Selector Field — In both BKP and DBG mode, PAGSEL selects the type of paging as shown in
DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and
11 will be interpreted as values of 00 and 01, respectively).
Comparator C Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown
in
Note: Comparator C can be used when the DBG module is configured for BKP mode. Extended addressing
Debug Comparator C Extended Register (DBGCCX)
0
7
Table 7-11
PAGSEL
comparisons for comparator C use PAGSEL and will operate differently to the way that comparator A and
B operate in BKP mode.
(256 — 16K pages)
DPAGE (reserved)
(256 — 4K pages)
EPAGE (reserved)
(256 — 1K pages)
Normal (64k)
Description
Figure 7-9. Debug Comparator C Extended Register (DBGCCX)
PPAGE
along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core.
0
6
Table 7-10. DBGCCX Field Descriptions
MC9S12C-Family / MC9S12GC-Family
Table 7-11. PAGSEL Decoding
0
5
EXTCMP[5:0] is compared to
EXTCMP[3:0] is compared to
EXTCMP[1:0] is compared to
address bits [21:16]
address bits [19:16]
address bits [17:16]
Rev 01.24
0
4
EXTCMP
Not used
Description
(2)
0
3
Chapter 7 Debug Module (DBGV1) Block Description
EXTCMP
(1)
DPAGE / XAB[21:14] becomes address
EPAGE / XAB[21:14] becomes address
PPAGE[7:0] / XAB[21:14] becomes
0
2
address bits [21:14]
No paged memory
bits [19:12]
bits [17:10]
Comment
0
1
1
Table
0
0
7-11.
203
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