HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 13

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

5.5
5.6
5.7
Section 6 Bus Controller (BSC).........................................................................101
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5.4.1
5.4.2
Interrupt Exception Handling Vector Table...................................................................... 85
Interrupt Control Modes and Interrupt Operation ............................................................. 88
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Usage Notes ...................................................................................................................... 99
5.7.1
5.7.2
5.7.3
5.7.4
Features............................................................................................................................. 101
Input/Output Pins .............................................................................................................. 104
Register Descriptions ........................................................................................................ 105
6.3.1
6.3.2
6.3.3
6.3.4
Bus Control ....................................................................................................................... 112
6.4.1
6.4.2
6.4.3
Bus Interface ..................................................................................................................... 124
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
Burst ROM Interface......................................................................................................... 145
6.6.1
6.6.2
Idle Cycle.......................................................................................................................... 147
Bus Arbitration.................................................................................................................. 148
6.8.1
6.8.2
6.8.3
External Interrupts ............................................................................................... 82
Internal Interrupts ................................................................................................ 84
Interrupt Control Mode 0 ..................................................................................... 90
Interrupt Control Mode 1 ..................................................................................... 92
Interrupt Exception Handling Sequence .............................................................. 94
Interrupt Response Times .................................................................................... 96
DTC Activation by Interrupt................................................................................ 97
Conflict between Interrupt Generation and Disabling ......................................... 99
Instructions that Disable Interrupts ...................................................................... 100
Interrupts during Execution of EEPMOV Instruction.......................................... 100
IRQ Status Registers (ISR16, ISR) ...................................................................... 100
Bus Control Register (BCR) ................................................................................ 105
Bus Control Register 2 (BCR2) ........................................................................... 106
Wait State Control Register (WSCR) .................................................................. 108
Wait State Control Register 2 (WSCR2) ............................................................. 110
Bus Specifications................................................................................................ 112
Advanced Mode................................................................................................... 122
I/O Select Signals................................................................................................. 123
Data Size and Data Alignment............................................................................. 124
Valid Strobes ....................................................................................................... 126
Basic Operation Timing in Normal Extended Mode ........................................... 127
Basic Operation Timing in Address-Data Multiplex Extended Mode ................. 135
Wait Control ........................................................................................................ 141
Basic Operation Timing....................................................................................... 145
Wait Control ........................................................................................................ 146
Overview.............................................................................................................. 148
Operation ............................................................................................................. 148
Bus Mastership Transfer Timing ......................................................................... 148
Rev. 3.00, 03/04, page xi of xl