HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 18

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

11.6 Interrupt Sources............................................................................................................... 298
11.7 Usage Notes ...................................................................................................................... 299
Section 12 8-Bit Timer (TMR).......................................................................... 305
12.1 Features............................................................................................................................. 305
12.2 Input/Output Pins.............................................................................................................. 308
12.3 Register Descriptions........................................................................................................ 309
12.4 Operation .......................................................................................................................... 322
12.5 Operation Timing.............................................................................................................. 323
12.6 TMR_0 and TMR_1 Cascaded Connection...................................................................... 326
12.7 Input Capture Operation ................................................................................................... 327
12.8 Interrupt Sources............................................................................................................... 329
Rev. 3.00, 03/04, page xvi of xl
11.5.4 Input Capture Input Timing ................................................................................. 292
11.5.5 Buffered Input Capture Input Timing .................................................................. 293
11.5.6 Timing of Input Capture Flag (ICF) Setting ........................................................ 294
11.5.7 Timing of Output Compare Flag (OCF) setting................................................... 295
11.5.8 Timing of FRC Overflow Flag (OVF) Setting..................................................... 295
11.5.9 Automatic Addition Timing................................................................................. 296
11.5.10 Mask Signal Generation Timing.......................................................................... 296
11.7.1 Conflict between FRC Write and Clear ............................................................... 299
11.7.2 Conflict between FRC Write and Increment........................................................ 300
11.7.3 Conflict between OCR Write and Compare-Match ............................................. 301
11.7.4 Switching of Internal Clock and FRC Operation................................................. 302
12.3.1 Timer Counter (TCNT)........................................................................................ 309
12.3.2 Time Constant Register A (TCORA) .................................................................. 310
12.3.3 Time Constant Register B (TCORB)................................................................... 310
12.3.4 Timer Control Register (TCR)............................................................................. 311
12.3.5 Timer Control/Status Register (TCSR)................................................................ 314
12.3.6 Input Capture Register (TICR) ............................................................................ 319
12.3.7 Time Constant Register C (TCORC)................................................................... 319
12.3.8 Input Capture Registers R and F (TICRR and TICRF)........................................ 319
12.3.9 Timer Input Select Register (TISR)..................................................................... 320
12.3.10 Timer Connection Register I (TCONRI) ............................................................. 320
12.3.11 Timer Connection Register S (TCONRS) ........................................................... 321
12.4.1 Pulse Output ........................................................................................................ 322
12.5.1 TCNT Count Timing ........................................................................................... 323
12.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 323
12.5.3 Timing of Timer Output at Compare-Match........................................................ 324
12.5.4 Timing of Counter Clear at Compare-Match....................................................... 324
12.5.5 TCNT External Reset Timing.............................................................................. 325
12.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 325
12.6.1 16-Bit Count Mode .............................................................................................. 326
12.6.2 Compare-Match Count Mode .............................................................................. 326