HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 185

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

(2) In Address-Data Multiplex Extended Mode
(a) Program Wait Mode: Program wait mode includes address wait and data wait.
256-kbyte extended area and IOS extended area:
Zero or one state of address wait T
data wait T
CP extended area:
Zero or one state of address wait T
data wait T
(b) Pin Wait Mode: When accessing the external address space, a specified number of wait states
T
is specified by the settings of the WC1 and WC0 bits (the WC21 and WC20 bits for the CP
extended area). If the WAIT pin is low at the falling edge of φ in the last T
another T
high.
Pin wait mode is useful when inserting four or more T
T
(c) Pin Auto-Wait Mode: A specified number of wait states T
and T
of φ in the last T
WC0 bits (the WC21 and WC20 bits for the CP extended area). Even if the WAIT pin is held low,
T
Pin auto-wait mode enables the low-speed memory interface only by inputting the chip select
signal to the WAIT pin.
Figure 6.26 shows an example of wait state insertion timing in pin wait mode.
DSW
DOW
DOW
can be inserted between the T
states to be inserted for each external device.
states are inserted only up to the specified number of states.
5
state when accessing the external address space if the WAIT pin is low at the falling edge
DOW
DSW
DSW
state is inserted. If the WAIT pin is held low, T
is inserted between T
is inserted between T
4
state. The number of wait states T
AW
AW
4
4
4
state and T
and T
and T
is inserted between T
is inserted between T
5
5
states.
states.
5
state of data state. The number of wait states T
DOW
DOW
is specified by the settings of the WC1 and
states, or when changing the number of
1
1
and T
and T
DOW
DOW
states are inserted until it goes
Rev. 3.00, 03/04, page 143 of 830
2
2
are inserted between the T
states. Zero to three states of
states. Zero to three states of
4
, T
DSW
, or T
DOW
state,
4
state
DSW