HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 242

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

8.5
Port 5 is an 8-bit I/O port. Port 5 pins also function as interrupt input pins, the PWMX output pin,
SCI_0, SCI_1, and SCI_2 input/output pins. Port 5 has the following registers.
• Port 5 data direction register (P5DDR)
• Port 5 data register (P5DR)
8.5.1
The individual bits of P5DDR specify input or output for the pins of port 5.
8.5.2
P5DR stores output data for the port 5 pins.
Rev. 3.00, 03/04, page 200 of 830
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
P57DDR
P56DDR
P55DDR
P54DDR
P53DDR
P52DDR
P51DDR
P50DDR
Bit Name
P57DR
P56DR
P55DR
P54DR
P53DR
P52DR
P51DR
P50DR
Port 5
Port 5 Data Direction Register (P5DDR)
Port 5 Data Register (P5DR)
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
If port 5 pins are specified for use as the general I/O
port, the corresponding port 5 pins are output ports
when the P5DDR bits are set to 1, and input ports
when cleared to 0.
Description
P5DR stores output data for the port 5 pins that are
used as the general output port.
If a port 5 read is performed while the P5DDR bits are
set to 1, the P5DR values are read. If a port 5 read is
performed while the P5DDR bits are cleared to 0, the
pin states are read.