HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 35

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Figure 25.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)....................... 790
Figure 25.7 External Clock Input Timing................................................................................... 790
Figure 25.8 Timing of External Clock Output Stabilization Delay Time ................................... 791
Figure 25.9 Subclock Input Timing ............................................................................................ 791
Figure 25.10 Reset Input Timing................................................................................................ 792
Figure 25.11 Interrupt Input Timing........................................................................................... 793
Figure 25.12 Basic Bus Timing/2-State Access.......................................................................... 795
Figure 25.13 Basic Bus Timing/3-State Access.......................................................................... 796
Figure 25.14 Basic Bus Timing/3-State Access with One Wait State ........................................ 797
Figure 25.15 Burst ROM Access Timing/2-State Access........................................................... 798
Figure 25.16 Burst ROM Access Timing/1-State Access........................................................... 799
Figure 25.17 Multiplex Bus Timing/Data 2-State Access .......................................................... 801
Figure 25.18 Multiplex Bus Timing/Data 3-State Access .......................................................... 801
Figure 25.19 I/O Port Input/Output Timing................................................................................ 804
Figure 25.20 FRT Input/Output Timing ..................................................................................... 804
Figure 25.21 FRT Clock Input Timing ....................................................................................... 804
Figure 25.22 8-Bit Timer Output Timing ................................................................................... 804
Figure 25.23 8-Bit Timer Clock Input Timing ........................................................................... 805
Figure 25.24 8-Bit Timer Reset Input Timing ............................................................................ 805
Figure 25.25 PWM, PWMX Output Timing .............................................................................. 805
Figure 25.26 SCK Clock Input Timing....................................................................................... 805
Figure 25.27 SCI Input/Output Timing (Clock Synchronous Mode) ......................................... 806
Figure 25.28 A/D Converter External Trigger Input Timing...................................................... 806
Figure 25.29 WDT Output Timing (RESO) ............................................................................... 806
2
Figure 25.30 I
C Bus Interface Input/Output Timing ................................................................. 808
Figure 25.31 LPC Interface (LPC) Timing................................................................................. 809
Figure 25.32 JTAG ETCK Timing ............................................................................................. 810
Figure 25.33 Reset Hold Timing ................................................................................................ 810
Figure 25.34 JTAG Input/Output Timing................................................................................... 810
Figure 25.35 Connection of VCL Capacitor............................................................................... 816
Appendix
Figure C.1 Package Dimensions (TFP-144) ............................................................................... 820
Rev. 3.00, 03/04, page xxxiii of xl