HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 368

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

12.6
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode
can be selected.
12.6.1
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with TMR_0 occupying the upper eight bits and TMR_1 occupying the lower eight bits.
• Setting of compare-match flags
• Counter clear specification
• Pin output
12.6.2
When bits CKS2 to CKS0 in TCR_1 are B′100, TCNT_1 counts the occurrence of compare-match
A for TMR_0. TMR_0 and TMR_1 are controlled independently. Conditions such as setting of the
CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in
accordance with the settings for each channel.
Rev. 3.00, 03/04, page 326 of 830
 The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs.
 The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs.
 If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match,
 The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot
 Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with
 Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with
the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare-
match occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when
counter clear by the TMI0 pin has been set.
be cleared independently.
the 16-bit compare-match conditions.
the lower 8-bit compare-match conditions.
TMR_0 and TMR_1 Cascaded Connection
16-Bit Count Mode
Compare-Match Count Mode