HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 477

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

This LSI has a six-channel I
a subset of the Philips I
controls the I
15.1
• Selection of addressing format or non-addressing format
• Conforms to Philips I
• Two ways of setting slave address (I
• Start and stop conditions generated automatically in master mode (I
• Selection of acknowledge output levels when receiving (I
• Automatic loading of acknowledge bit when transmitting (I
• Wait function in master mode (I
• Wait function (I
• Interrupt sources
• Selection of 32 internal clocks (in master mode)
• Direct bus drive
IFIIC50C_000020030700
 I
 Clocked synchronous serial format: non-addressing format without acknowledge bit, for
 A wait can be inserted by driving the SCL pin low after data transfer, excluding
 The wait can be cleared by clearing the interrupt flag.
 A wait request can be generated by driving the SCL pin low after data transfer.
 The wait request is cleared when the next transfer becomes possible.
 Data transfer end (including when a transition to transmit mode with I
 Address match: when any slave address matches or the general call address is received in
 Arbitration loss
 Start condition detection (in master mode)
 Stop condition detection (in slave mode)
 PinsSCL0 to SCL5 and SDA0 to SDA5 (normally NMOS push-pull outputs) function
master operation only
acknowledgement.
when ICDR data is transferred, or during a wait state)
slave receive mode with I
arbitration)
as NMOS open-drain outputs when the bus drive function is selected.
2
C bus format: addressing format with acknowledge bit, for master/slave operation
Features
2
C bus differs partly from the Philips configuration, however.
2
C bus format)
Section 15 I
2
C bus (inter-IC bus) interface functions. The register configuration that
2
C bus interface (I
2
C bus interface (IIC). The I
2
C bus format (including address reception after loss of master
2
C bus format)
2
C bus format)
2
2
C Bus Interface (IIC)
C bus format)
2
C bus interface conforms to and provides
2
C bus format)
2
C bus format)
Rev. 3.00, 03/04, page 435 of 830
2
C bus format)
2
C bus format occurs,