HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 508
HD64F2168VTE33
Manufacturer Part Number
HD64F2168VTE33
Description
Manufacturer
Renesas Electronics America
Datasheet
1.HD64F2168VTE33.pdf
(876 pages)
Specifications of HD64F2168VTE33
Cpu Family
H8S
Device Core Size
16/32Bit
Frequency (max)
33MHz
Interface Type
I2C/IrDA/SCI
Program Memory Type
Flash
Program Memory Size
256KB
Total Internal Ram Size
40KB
# I/os (max)
106
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
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Quantity
Price
Company:
Part Number:
HD64F2168VTE33V
Manufacturer:
Renesas
Quantity:
8 400
Company:
Part Number:
HD64F2168VTE33V
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RENESAS
Quantity:
112
Part Number:
HD64F2168VTE33V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Table 15.8 I
Rev. 3.00, 03/04, page 466 of 830
Symbol
S
SLA
R/W
A
DATA
P
SDA
SCL
S
Description
Start condition. The master device drives SDA from high to low while SCL is high
Slave address. The master device selects the slave device.
Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The
slave device returns acknowledge in master transmit mode, and the master device
returns acknowledge in master receive mode.)
Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in
ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR.
Stop condition. The master device drives SDA from low to high while SCL is high
2
C Bus Data Format Symbols
SLA
1–7
R/W
8
A
9
Figure 15.5 I
1–7
DATA
2
C Bus Timing
8
A
9
1–7
DATA
8
A/A
9
P
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