HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 52

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Rev. 3.00, 03/04, page 10 of 830
Type
Address/
data
multiplex
bus
Bus control
Interrupts
Boundary
scan
Symbol
AD15 to
AD8
AD7 to
AD0
WAIT
RD
HWR
LWR
AS/IOS
CS256
CPCS1
AH
NMI
IRQ15 to
IRQ0
ExIRQ15
to ExIRQ2
ETRST
ETMS
ETDO
ETDI
ETCK
Pin No.
96 to 103
104 to 110,
112
17
21
20
24
19
17
22
23
11
6, 5, 137,
136, 134,
133, 15,
16, 4 to 2,
138, 132 to
129
43 to 50
75 to 70
91
87
88
89
90
I/O
Input/
Output
Input
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Output
Input
Input
Name and Function
8-bit, upper 16-bit bus
Lower 16-bit bus
Requests insertion of a wait state in the bus cycle
when accessing an external 3-state address
space.
This pin is low when the external address space
is being read.
This pin is low when the external address space
is to be written to, and the upper half of the data
bus is enabled.
This pin is low when the external address space
is to be written to, and the lower half of the data
bus is enabled.
This pin is low when address output on the
address bus is valid.
Indicates that the 256k-byte area from H'F80000
to H'FBFFFF is accessed.
Indicates that the CP extended area is accessed.
Address latch signal for address/data multiplex
bus.
Nonmaskable interrupt request input pin
These pins request a maskable interrupt.
Selectable to which pin of IRQn or ExIRQn to
insert IRQ15 to IRQ2 interrupts.
Boundary scan interface pins