HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 542
HD64F2168VTE33
Manufacturer Part Number
HD64F2168VTE33
Description
Manufacturer
Renesas Electronics America
Datasheet
1.HD64F2168VTE33.pdf
(876 pages)
Specifications of HD64F2168VTE33
Cpu Family
H8S
Device Core Size
16/32Bit
Frequency (max)
33MHz
Interface Type
I2C/IrDA/SCI
Program Memory Type
Flash
Program Memory Size
256KB
Total Internal Ram Size
40KB
# I/os (max)
106
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant
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Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in
8. Notes on start condition issuance for retransmission
Rev. 3.00, 03/04, page 500 of 830
Internal clock
Figure 15.30 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. Write the
transmit data to ICDR after the start condition for retransmission is issued and then the start
condition is actually generated.
BBSY bit
ICXR.
SDA
SCL
Master receive mode
Bit 0
8
Figure 15.29 Notes on Reading Master Receive Data
(write 0 to BBSY and SCP)
for issuing stop condition
Execution of instruction
A
9
disabled period
ICDR read
Confirmation of stop
condition issuance
(read BBSY = 0)
Stop condition
(a)
Start condition
issuance
Start condition
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