HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 555

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HD64F2168VTE33

Manufacturer Part Number
HD64F2168VTE33
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F2168VTE33

Cpu Family
H8S
Device Core Size
16/32Bit
Frequency (max)
33MHz
Interface Type
I2C/IrDA/SCI
Program Memory Type
Flash
Program Memory Size
256KB
Total Internal Ram Size
40KB
# I/os (max)
106
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant

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Bit
4
3
Bit Name Initial Value Slave Host Description
FGA20E
SDWNE
0
0
R/W
R/W
R/W
Fast A20 Gate Function Enable
Enables or disables the fast A20 gate function. When
the fast A20 gate is disabled, the normal A20 gate
can be implemented by firmware operation of the
PD3 output.
When the fast A20 gate function is enabled, the DDR
bit for PD3 must not be set to 1.
0: Fast A20 gate function disabled
1: Fast A20 gate function enabled
LPC Software Shutdown Enable
Controls LPC interface shutdown. For details of the
LPC shutdown function, and the scope of
initialization by an LPC reset and an LPC shutdown,
see section 16.4.6, LPC Interface Shutdown
Function (LPCPD).
0: Normal state, LPC software shutdown setting
enabled
[Clearing conditions]
1: LPC hardware shutdown state setting enabled
[Setting condition]
Other function of the pin is enabled
GA20 output internal state is initialized to 1
GA20 pin output is open-drain (external VCC
pull-up resistor required)
Writing 0
LPC hardware reset or LPC software reset
LPC hardware shutdown release (rising edge of
LPCPD signal)
Hardware shutdown state when LPCPD signal is
low
Writing 1 after reading SDWNE = 0
Rev. 3.00, 03/04, page 513 of 830

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