HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 561

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Bit
4
3
2
Bit Name Initial Value Slave Host Description
ABRT
IBFIE3
IBFIE2
0
0
0
R/W
R/W
R/(W)* 
R/W


LPC Abort Interrupt Flag
Interrupt flag that generates an ERRI interrupt when
a forced termination (abort) of an LPC transfer cycle
occurs.
0: [Clearing conditions]
•
•
•
•
•
1: [Setting condition]
•
IBFI3 Interrupt Enable
Enables or disables IBFI3 interrupt to the slave
processor (this LSI).
0: Input data register IDR3 and TWR receive
1: [When TWRE in LADR3 = 0]
IDR2 Receive Completion Interrupt Enable
Enables or disables IBFI2 interrupt to the slave
processor (this LSI).
0: Input data register IDR2 receive completed
1: Input data register IDR2 receive completed
[When TWRE in LADR3 = 1]
completed interrupt requests and SMIC mode and
BT mode interrupt requests are disabled
Input data register IDR3 receive completed
interrupt request and SMIC mode and BT mode
interrupt requests are enabled
Input data register IDR3 and TWR receive
completed interrupt requests and SMIC mode and
BT mode interrupt requests are enabled
interrupt requests disabled
interrupt requests enabled
Writing 0 after reading ABRT = 1
LPC hardware reset
LPC software reset
LPC hardware shutdown
LPC software shutdown
LFRAME pin falling edge detection during LPC
transfer cycle
Rev. 3.00, 03/04, page 519 of 830