HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 568

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

16.3.5
LADR12H and LADR12L are temporary registers for accessing internal registers LADR1H,
LADR1L, LADR2H, and LADR2L.
When the LADR12SEL bit in HICR4 is 0, LPC channel 1 host addresses (LADR1H, LADR1L)
are set through LADR12. The contents of the address field in LADR1 must not be changed while
channel 1 is operating (while LPC1E is set to 1).
When the LADR12SEL bit is 1, LPC channel 2 host addresses (LADR2H, LADR2L) are set
through LADR12. The contents of the address field in LADR2 must not be changed while channel
2 is operating (while LPC2E is set to 1).
Table 16.2 shows the initial value of each register. Table 16.3 shows the host register selection in
address match determination. Table 16.4 shows the slave selection internal registers in slave (this
LSI) access.
Table 16.2 LADR1, LADR2 Initial Values
Table 16.3 Host Register Selection
Rev. 3.00, 03/04, page 526 of 830
Register Name
LADR1
LADR2
Bits 15 to 3
LADR1 (bits 15 to 3) 0
LADR1 (bits 15 to 3) 1
LADR1 (bits 15 to 3) 0
LADR1 (bits 15 to 3) 1
LADR2 (bits 15 to 3) 0
LADR2 (bits 15 to 3) 1
LADR2 (bits 15 to 3) 0
LADR2 (bits 15 to 3) 1
LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)
Bit 2 Bit 1
I/O Address
Initial Value
H'0060
H'0062
LADR1 (bit 1) LADR1 (bit 0) I/O write
LADR1 (bit 1) LADR1 (bit 0) I/O write
LADR1 (bit 1) LADR1 (bit 0) I/O read
LADR1 (bit 1) LADR1 (bit 0) I/O read
LADR2 (bit 1) LADR2 (bit 0) I/O write
LADR2 (bit 1) LADR2 (bit 0) I/O write
LADR2 (bit 1) LADR2 (bit 0) I/O read
LADR2 (bit 1) LADR2 (bit 0) I/O read
Bit 0
Description
I/O address of channel 1
I/O address of channel 2
Transfer
Cycle
Host Register Selection
IDR1 write (data),
C/D1 ← 0
IDR1 write (command),
C/D1 ← 1
ORD1 read
STR1 read
IDR2 write (data),
C/D2 ← 0
IDR2 write (command),
C/D2 ← 1
ODR2 read
STR2 read