HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 619

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

16.4.6
The LPC interface can be placed in the shutdown state according to the state of the LPCPD pin.
There are two kinds of LPC interface shutdown state: LPC hardware shutdown and LPC software
shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the LPC
software shutdown state is controlled by the SDWNB bit. In both states, a part of the LPC
interface enters the reset state by itself, and is no longer affected by external signals other than the
LRESET and LPCPD signals.
Placing the slave processor in sleep mode or software standby mode is effective in reducing
current dissipation in the shutdown state. If software standby mode is set, some means must be
provided for exiting software standby mode before clearing the shutdown state with the LPCPD
signal.
If the SDWNE bit has been set to 1 beforehand, the LPC hardware shutdown state is entered at the
same time as the LPCPD signal falls, and prior preparation is not possible. If the LPC software
shutdown state is set by means of the SDWNB bit, on the other hand, the LPC software shutdown
state cannot be cleared at the same time as the rise of the LPCPD signal. Taking these points into
consideration, the following operating procedure uses a combination of LPC software shutdown
and LPC hardware shutdown.
1. Clear the SDWNE bit to 0.
2. Set the ERRIE bit to 1 and wait for an interrupt by the SDWN flag.
3. When an ERRI interrupt is generated by the SDWN flag, check the LPC interface internal
4. Set the SDWNB bit to 1 to set LPC software shutdown mode.
5. Set the SDWNE bit to 1 and make a transition to LPC hardware shutdown mode. The SDWNB
6. Check the state of the LPCPD signal to make sure that the LPCPD signal has not risen during
7. Place the slave processor in sleep mode or software standby mode as necessary.
8. If software standby mode has been set, exit software standby mode by some means
9. When a rising edge is detected in the LPCPD signal, the SDWNE bit is automatically cleared
Table 16.8 shows the scope of LPC interface pin shutdown.
status flags and perform any necessary processing.
bit is cleared automatically.
steps 3 to 5. If the signal has risen, clear the SDWNE bit to 0 to return to the state in step 1.
independent of the LPC.
to 0. If the slave processor has been placed in sleep mode, the mode is exited by means of
LRESET signal input, on completion of the LPC transfer cycle, or by some other means.
LPC Interface Shutdown Function (LPCPD)
Rev. 3.00, 03/04, page 577 of 830