HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 629

no-image

HD64F2168VTE33

Manufacturer Part Number
HD64F2168VTE33
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F2168VTE33

Cpu Family
H8S
Device Core Size
16/32Bit
Frequency (max)
33MHz
Interface Type
I2C/IrDA/SCI
Program Memory Type
Flash
Program Memory Size
256KB
Total Internal Ram Size
40KB
# I/os (max)
106
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2168VTE33
Manufacturer:
HIT
Quantity:
1 000
Part Number:
HD64F2168VTE33V
Manufacturer:
Renesas
Quantity:
8 400
Part Number:
HD64F2168VTE33V
Manufacturer:
RENESAS
Quantity:
112
Part Number:
HD64F2168VTE33V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
16.6
16.6.1
The LPC operation stop or enable can be specified by the module stop control register. With the
initial value, LPC operation will stop. Releasing module stop mode enables access to the register.
For details see section 23, Power-Down Modes.
16.6.2
The LPC interface provides buffering of asynchronous data from the host processor and slave
processor (this LSI), but an interface protocol that uses the flags in STR is required to avoid data
contention. For example, if the host and slave processor both try to access IDR or ODR at the
same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be
used to allow access only to data for which writing has finished.
Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data
registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing
to TWR0, MWMF and SWMF must be used to confirm that the right to access TWR1 to TWR15
has been obtained.
Table 16.13 shows the host address example of registers LADR3, IDR3, ODR3, STR3,
TWR0MW, TWR0SW, and TWR1 to TWR15.
Usage Notes
Module Stop Setting
Usage Note of LPC Interface
Rev. 3.00, 03/04, page 587 of 830

Related parts for HD64F2168VTE33