HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 96

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

3.2
The following registers are related to the operating mode. For details on the bus control register
(BCR), see section 6.3.1, Bus Control Register (BCR), and for details on bus control register 2
(BCR2), see section 6.3.2, Bus Control Register 2 (BCR2).
• Mode control register (MDCR)
• System control register (SYSCR)
• Serial timer control register (STCR)
3.2.1
MDCR is used to set an operating mode and to monitor the current operating mode.
Note:
Rev. 3.00, 03/04, page 54 of 830
Bit
7
6
to
3
2
1
0
Bit Name
EXPE
—
MDS2
MDS1
MDS0
*
Register Descriptions
Mode Control Register (MDCR)
The initial values are determined by the settings of the MD2, MD1, and MD0 pins.
0
All 0
—*
—*
—*
Initial Value
R/W
R
R
R
R
R/W
Description
Extended Mode Enable
Specifies extended mode.
0: Single-chip mode
1: Extended mode
Reserved
Mode Select 2 to 0
These bits indicate the input levels at mode pins (MD2,
MD1, and MD0) (the current operating mode). Bits
MDS2, MDS1, and MDS0 correspond to MD2, MD1,
and MD0, respectively. MDS2 to MDS0 are read-only
bits and they cannot be written to. The mode pin (MD2,
MD1, and MD0) input levels are latched into these bits
when MDCR is read. These latches are canceled by a
reset.