PCD3316T NXP Semiconductors, PCD3316T Datasheet - Page 11

• Manufacturer Part Number: PCD3316T
• Manufacturer: NXP Semiconductors

Specifications of PCD3316T

• Process Technology: CMOS
• Operating Frequency (max): 3580kHz
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Philips Semiconductors
9397 750 04824
Product specification
7.12.2 START and STOP conditions
7.12.3 Bit transfer
7.12.4 Acknowledge
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition
(S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a
STOP condition (P); see
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time will be interpreted as a control signal; see
The number of data bytes transferred between the START and the STOP conditions
from the transmitter to the receiver is unlimited. Each byte of eight bits is followed by
an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the
transmitter during which time the master generates an extra acknowledge-related
clock pulse.
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte. Also a master receiver must generate an acknowledge after
the reception of each byte that has been clocked out of the slave transmitter.
Fig 9. I
Fig 10. START and STOP conditions for the I
Fig 11. I
SDA
SCL
TRANSMITTER /
2
2
SDA
SCL
RECEIVER
C-bus configuration.
C-bus bit transfer.
MASTER
START condition
SDA
SCL
S
11 March 1999
Figure
RECEIVER
SLAVE
10.
data valid
data line
stable;
TRANSMITTER /
RECEIVER
SLAVE
allowed
change
of data
2
C-bus.
Figure
TRANSMITTER
MASTER
STOP condition
11.
© Philips Electronics N.V. 1999. All rights reserved.
MBA607
P
PCD3316
CIDCW receiver
MBA608
TRANSMITTER /
RECEIVER
MASTER
SDA
SCL
MBA605
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