PXAS30KBA NXP Semiconductors, PXAS30KBA Datasheet - Page 22

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PXAS30KBA

Manufacturer Part Number
PXAS30KBA
Description
Microcontrollers (MCU) XA 16BIT 1KR/ADC/I2C ROMLESS 277Q1
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PXAS30KBA

Data Bus Width
16 bit
Program Memory Type
ROM
Data Ram Size
1024 B
Interface Type
UART, I2C
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
50
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
SOT-188
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / Rohs Status
 Details
Other names
PXAS30KBA,512

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Philips Semiconductors
2000 Dec 01
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
2
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. In that case, the reset or inactive value of the new bit will be
** f
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. In that case, the reset or inactive value of the new bit will be
Symbol
CIDL
WDTE
CPS1
CPS0
ECF
Symbol
CF
CR
CCF4
CCF3
CCF2
CCF1
CCF0
Each of CCF4 through CCF0 generates its own interrupt, and has its own interrupt vector.
C, 2 UARTs, 16 MB address range
0, and its active value will be 1. The value read from a reserved bit is indeterminate.
0, and its active value will be 1. The value read from a reserved bit is indeterminate.
OSC
= oscillator frequency
Bit:
Bit Addressable
Bit:
Function
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
Not implemented, reserved for future use.*
PCA Count Pulse Select bit 1.
PCA Count Pulse Select bit 0.
CPS1
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
Function
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
Not implemented, reserved for future use*.
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
0
1
1
CMOD Address = 490H
CCON Address = 41AH
CIDL
7
CF
7
CPS0
X
0
1
WDTE
PCA Timer Count Source
TClk (Osc/4, Osc/16, or Osc/64)
Timer 0 overflow
ECI (PCA External Clock Input (max rate = Osc/4)
CR
6
6
Figure 11. CCON: PCA Counter Control Register
Figure 10. CMOD: PCA Counter Mode Register
5
5
CCF4
4
4
22
CCF3
3
3
CPS1
CCF2
2
2
CCF1
CPS0
1
1
CCF0
ECF
0
0
Reset Value = 00H
Reset Value = 00H
Preliminary specification
XA-S3
SU01306
SU01307

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