UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 259

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

13.2 A/D Converter Configuration
(1) Successive approximation register (SAR)
(2) A/D conversion result register 0 (ADCR0)
(3) Sample & hold circuit
(4) Voltage comparator
(5) Series resistor string
The A/D converter consists of the following hardware.
Caution
This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from
the series resistor string, and holds the result from the most significant bit (MSB).
When up to the least significant bit (LSB) is held (end of A/D conversion), the SAR contents are transferred to
A/D conversion result register 0 (ADCR0).
The ADCR0 is an 8-bit register that stores the A/D conversion result. Each time A/D conversion ends, the
conversion result is loaded from the successive approximation register.
ADCR0 is read by an 8-bit memory manipulation instruction.
RESET input clears ADCR0 to 00H.
The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D
conversion is started and holds the sampled analog input voltage value during A/D conversion.
The voltage comparator compares the sampled analog input voltage to the series resistor string output voltage.
The series resistor string is connected between AV
the analog input.
When writing is performed to A/D converter mode register 0 (ADM0) and analog input channel
specification register 0 (ADS0), the contents of ADCR0 may become undefined. Read the
conversion result following conversion completion before writing to ADM0, ADS0. Using a
timing other than the above may cause an incorrect conversion result to be read.
CHAPTER 13 8-BIT A/D CONVERTER ( PD780024A, 780024AY SUBSERIES)
Analog input
Hardware trigger input
Registers
Control registers
Item
Table 13-1. A/D Converter Configuration
8 channels (ANI0 to ANI7)
1 (ADTRG)
Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)
A/D converter mode register 0 (ADM0)
Analog input channel specification register 0 (ADS0)
User’s Manual U14046EJ5V0UD
REF
and AV
Configuration
SS
, and generates a voltage to be compared to
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