STA2064N STMicroelectronics, STA2064N Datasheet - Page 6

• Manufacturer Part Number: STA2064N
• Description: IC APPL PROCESSOR 289TFBGA
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STA2064N

• Applications: GPS
• Core Processor: ARM11
• Program Memory Type: -
• Controller Series: Cartesio™
• Ram Size: 8K x 32
• Interface: AC97, CAN, I²C, MSP, MMC/SD, SPDIF, SSP, UART, USB
• Number Of I /o: 65
• Voltage - Supply: 1.8 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11636

System description
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10
2.4
2.4.1
6/19
Real-time clock (RTC)
The RTC provides a one second resolution clock. This keeps time when the system is
inactive and can be used to wake the system up when a programmed ‘alarm’ time is
reached. It has a clock trimming feature to compensate the drift of the 32.768 kHz crystal.
Real-time timer (RTT)
The RTT has the possibility of being clocked off. This reduces the always_on domain
consumption during Deep Sleep. By default the RTT has its clock enabled.
Always_ON supply
The “Always_ON” domain retains its two separate supplies, one for the core logic (V
and one for the IOs (V
The V
lowest consumption possible, can also be configured as low as 1.0 ±10%V when the device
is in deep-sleep.
Enhanced function timer (EFT)
STA2064 features 4 16-bit EFTs. Each of the four EFT timers has a 16-bit free-running
counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse
counter function, and a PWM channel with selectable frequency.
Watchdog timer (WDT)
This OS resource is used to trigger a system reset in the event of software failure.
Memory interfaces
SD/MMC
STA2064 features two SD/SDIO/MMC interfaces up to 52 MHz / one up to 8-bit data, the
other up to 4-bit data. The main clock available to the peripherals is:
●
●
●
The peripheral is compliant to the following standards:
●
●
●
PLL2CLK/13 (when PLL2CLK is 624 MHz and SRC_MMC52 = 0, 48 MHz will be
generated)
PLL2CLK/12 (when PLL2CLK is 624 MHz and SRC_MMC = 1, 52 MHz will be
generated)
PLL2CLK/9 (when PLL2CLK is 432 MHz, 48 MHz will be generated)
MMC 4.4
SD 2.0/Part 1 - Physical Layer
SD 2.0/Part E1 - SDIO Specification
DDON
supply is equal to V
IOON
).
Doc ID 16057 Rev 3
DD
during normal operation but, with the goal of reaching the
STA2064
DDON
)