IS43DR16160A-25EBLI ISSI, Integrated Silicon Solution Inc, IS43DR16160A-25EBLI Datasheet - Page 17

• Manufacturer Part Number: IS43DR16160A-25EBLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43DR16160A-25EBLI

• Lead Free Status / Rohs Status: Compliant

IS43/46DR83200A, IS43/46DR16160A
Timing Parameters by Speed Grade (DDR2-400 and DDR2-533)
(For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.)
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
05/24/2011
Parameter
Clock cycle time, CL=x
CK HIGH pulse width
CK LOW pulse width
DQS latching rising transitions to associated clock
edges
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input HIGH pulse width
DQS input LOW pulse width
Write preamble
Write postamble
Address and control input setup time
Address and control input hold time
Control & Address input pulse width for each input
DQ and DM input setup time (differential strobe)
DQ and DM input hold time (differential strobe)
DQ and DM input setup time (single-ended strobe)
DQ and DM input hold time (single-ended strobe)
DQ and DM input pulse width for each input
DQ output access time from CK/CK
DQS output access time from CK/ CK
Data-out high-impedance time from CK/ CK
DQS(DQS) low-impedance time from CK/ CK
DQ low-impedance time from CK/ CK
DQS-DQ skew for DQS and associated DQ signals
CK half pulse width
DQ hold skew factor
DQ/DQS output hold time from DQS
Read preamble
Read postamble
tDS1(base)
tDH1(base)
tDS(base)
tDH(base)
tLZ(DQS)
tIS(base)
tIH(base)
Symbol
tDQSCK
tLZ(DQ)
tWPRE
tDQSS
tDQSH
tWPST
tDQSQ
tDQSL
tRPRE
tRPST
tDIPW
tQHS
tDSS
tDSH
tIPW
tCH
tQH
tCK
tAC
tHZ
tHP
tCL
min (tCL,
tAC min tAC max tAC min
2 x tAC
- 0.25
tQHS
Min.
5000
- 600
- 500
tHP -
tCH)
0.48
0.48
0.35
0.35
0.35
0.35
350
475
150
275
min
0.2
0.2
0.4
0.6
0.9
0.4
25
25
DDR2-400
–
–
–
tAC max
tAC max
+ 600
+ 500
Max.
8000
0.52
0.52
0.25
350
450
0.6
1.1
0.6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
tHP - tQHS
min (tCL,
2 x tAC
- 0.25
Min.
3750
- 500
- 450
tCH)
0.48
0.48
0.35
0.35
0.35
0.35
250
375
100
225
- 25
- 25
min
DDR2-553
0.2
0.2
0.4
0.6
0.9
0.4
–
–
–
+ 500
+ 450
8000
Max
0.52
0.52
0.25
max
max
max
400
tAC
tAC
tAC
300
1.1
0.6
0.6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Units Notes
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
15
10
5, 7, 9,
22
5, 7, 9,
23
6, 7, 8,
20, 28
6, 7, 8,
21, 28
6, 7, 8,
25
6, 7, 8,
26
18
18
18
13
11,12
12
19
19
17