SI3019-F-FT Silicon Laboratories Inc, SI3019-F-FT Datasheet - Page 38

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SI3019-F-FT

Manufacturer Part Number
SI3019-F-FT
Description
IC VOICE DAA GCI/PCM/SPI 16TSSOP
Manufacturer
Silicon Laboratories Inc
Type
Chipsetr
Datasheets

Specifications of SI3019-F-FT

Package / Case
16-TSSOP
Function
Data Access Arrangement (DAA)
Interface
GCI, PCM, SPI
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
8.5mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Includes
Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
Product
Modem Chip
Supply Voltage (min)
3 V
Supply Current
8.5 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Si3050
The PLL clock synthesizer settles quickly after powerup.
However, the settling time depends on the PCLK
frequency and it can be approximately predicted by the
following equation:
For all valid PCLK frequencies listed above, the default
line sample rate is 8 kHz. This sample rate can be
increased to 16 kHz by setting the HSSM bit
(Register 7, bit 3). Regardless of the sample rate
frequency, the serial data communication rate of the
PCM and GCI highways remains 8 kHz. When the
16 kHz sample rate is selected, additional timeslots in
the PCM or GCI highway are used to transfer the
additional data.
5.31. Communication Interface Mode
The Si3050 supports two communication interface
protocols:
38
PCLK
Selection
÷N
T
settle
= 64/F
PCLK
PFD
Note: Values shown are the states of the pins at the rising edge of
SCLK
Table 19. PCM or GCI Highway Mode Selection
1
0
0
RESET.
Figure 27. PLL Clock Synthesizer
SDI
X
0
1
Internal PLL
Register
DIV M
Rev. 1.2
A pin-strapping method (specifically, the state of SCLK
on power-up [reset]) is used to select between the two
communication interface protocols. Tables 18 and 19
specify how to select a communication mode, and how
the various pins are used in each mode.
When operating in PCM/SPI mode, the GCI control
register should not be written (i.e., Register 42 must
each remain set at 0000_0000 when using the PCM/
SPI highway mode). Similarly, when operating in GCI
highway mode the PCM registers should not be written
(i.e., Registers 33–37 must remain set to 0000_0000
when using the GCI highway mode).
B2 Channel used
B1 Channel used
PCM/SPI mode where data and control information
transmission/reception occurs across separate
buses (PCM highway for data, and SPI port for
control).
GCI mode where data and control information is
multiplexed and transmission/reception occurs
across the GCI highway bus.
Mode Selected
PCM Mode
GCI Mode,
GCI Mode,
VCO
÷2
÷2
16.384 MHz

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