SI3063-F-FS Silicon Laboratories Inc, SI3063-F-FS Datasheet - Page 16

• Manufacturer Part Number: SI3063-F-FS
• Description: IC DAA ENH GLOB LINE-SIDE 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Type: Integrated Direct Access Arrangementr

Specifications of SI3063-F-FS

• Package / Case: *
• Function: Direct Access Arrangement (DAA)
• Number Of Circuits: 1
• Current - Supply: 9mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: Billing Tone Detection, Line Voltage Monitor, Loop Current Monitor, Overload Detection, Ring Detector
• Supply Current: 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power (watts): -
• Interface: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Si306x
6.2. Power Supplies
The Si306x line-side device derives its power from two
sources: The system-side module and the telephone
line. The integrated system-side module supplies power
over the patented capacitive isolation link between the
two
communicate with the system-side module while on-
hook and perform other on-hook functions such as line
voltage monitoring. When off-hook, the line-side device
also derives power from the line current supplied from
the telephone line. This feature is exclusive to DAAs
from Silicon Laboratories and allows the most cost
effective
maintaining robust performance over all line conditions.
6.3. Initialization
When the integrated system-side module is powered
up, assert the RESET pin. When the RESET pin is
deasserted, the registers have default values. This reset
condition guarantees the line-side device is powered
down without the possibility of loading the line (i.e., off-
hook). An example initialization procedure is outlined in
the following list:
1. Program the desired sample rate with the Sample
2. Wait until the line-side PLL is locked. This time is
3. Write a 00H into the DAA Control Register
4. Set the required line interface parameters MINI[1:0],
When this procedure is complete, the Si306x is ready
for ring detection and off-hook.
6.4. Isolation Barrier
The Si306x achieves an isolation barrier through low-
cost, high-voltage capacitors in conjunction with Silicon
Laboratories’ proprietary signal processing techniques.
These techniques eliminate signal degradation from
capacitor mismatches, common mode interference, or
noise coupling. As shown in "3. Typical Application
Schematic" on page 9, the C1, C2, C8, and C9
capacitors isolate the integrated system-side module
from the line-side device. Transmit, receive, control, ring
detect, and caller ID data are passed across this barrier.
Y2 class capacitors can be used to achieve surge
performance of 5 kV or greater.
The proprietary capacitive communications link is
disabled by default. To enable it, the PDL bit
16
Rate Control Register (Register 7).
normally between 100 µs and 1 ms from the
application of MCLK.
(Register 6) to power up the line-side device.
ILIM, DCR, ACT and ACT2, OHS, RT, RZ, ATX[2:0]
and ARX[2:0] as defined by “Country Specific
Register Settings” shown in Table 7.
devices,
implementation
allowing
the
for
line-side
a
DAA
device
while
still
Rev. 0.9
to
(Register 6, bit 4) must be cleared. No communication
between the system-side and line-side can occur until
this bit is cleared.
6.5. Power Management
The DAA supports four basic power management
operation modes. The modes are normal operation,
reset operation, sleep mode, and full powerdown mode.
PDN and PDL bits (Register 6) control the power
management modes.
On powerup, or following a reset, the DAA is in reset
operation. The PDL bit is set, and the PDN bit is
cleared. The system-side module is operational, except
for the communications link. No communication
between the system-side module and the Si306x line-
side device can occur during reset operation. Bits
associated with the line-side device are not valid in this
mode.
The most common mode of operation is the normal
operation. In this mode, the PDL and PDN bits are
cleared.
communications link is passing information between the
Si306x and the line-side device.
The Si306x supports a low-power sleep mode that
supports the wake-up-on-ring feature of many modems.
The clock generator registers 7, 8, and 9 must be
programmed with valid,
enabling sleep mode. The PDN bit must be set and the
PDL bit cleared. When the Si306x is in sleep mode, the
host processor clock signal must remain active to
support ring validation and wake-on-ring features. In low
power sleep mode, the system-side module is non-
functional except for the communications link and the
RGDT signal. To take the Si306x out of sleep mode, the
system-side module should be reset.
In summary, the powerdown/up sequence for sleep
mode is as follows:
1. Ensure that Registers 7, 8, and 9 must have valid
2. Set the PDN bit (Register 6, bit 3) and clear the PDL
3. The system-side module clock must stay active.
4. Reset the system-side module.
5. Program registers to the desired settings.
The Si306x also supports an additional powerdown
mode. When both the PDN (Register 6, bit 3) and PDL
(Register 6, bit 4) bits are set, the chipset enters a
complete powerdown mode and draws negligible
current (deep sleep mode). In this mode, the ring detect
function does not operate. Normal operation is restored
by the same process for taking the DAA out of sleep
mode.
non-zero values.
bit (Register 6, bit 4).
The
DAA
is
non-zero values before
operational
and
the