PEB 3081 H V1.4 Infineon Technologies, PEB 3081 H V1.4 Datasheet - Page 138

• Manufacturer Part Number: PEB 3081 H V1.4
• Description: IC S-BUS INTERFACE EXT MQFP44
• Manufacturer: Infineon Technologies

Specifications of PEB 3081 H V1.4

• Function: S / T Bus Interface Transceiver
• Interface: IOM-2, ISDN, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-QFP
• Includes: D-Channel Access Control, Monitor Channel Handler
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3081HV1.4XT; PEB3081HV14XP; SP000007583; SP000007584

ISTATR
MASKTR
For all interrupts in the ISTATR register the following logical states are defined:
0: Interrupt is not acitvated
1: Interrupt is acitvated
x ... Reserved
Bits set to “1” in this bit position must be ignored.
LD ... Level Detection
Any receive signal has been detected on the line. This bit is set to “1” (i.e. an interrupt is
generated if not masked) as long as any receiver signal is detected on the line.
RIC ... Receiver INFO Change
RIC is activated if one of the TR_STA bits RINF or ICV has changed. This bit is reset by
reading the TR_STA register.
SQC ... S/Q-Channel Change
A change in the received S-channel (TE) or Q-channel (NT) has been detected. The new
code can be read from the SQRxx bits of registers SQRR1-3 within the duration of the
next multiframe (5 ms). This bit is reset by a read access to the corresponding SQRRx
register.
SQW ... S/Q-Channel Writable
The S/Q channel data for the next multiframe is writable.
The register for the Q (S) bits to be transmitted (received) has to be written (read) within
the duration of the next multiframe (5 ms). This bit is reset by writing register SQXRx.
4.1.18
Value after reset: FF
Data Sheet
7
7
MASKTR - Mask Transceiver Interrupt
0
1
H
1
x
x
1
1
x
138
LD
LD
RIC
RIC
Detailed Register Description
SQC
SQC
0
0
SQW
SQW
RD/WR (39)
PEB 3081
2003-02-04
SBCX-X
RD (38)